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參數(shù)資料
| 型號： | LTC4215CUFD-3 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 307K |
| 代理商： | LTC4215CUFD-3 |
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LTC4215-1/LTC4215-3
15
421513fc
Board Present Change of State
Whenever the EN pin toggles, bit D4 is set to indicate a
change of state. When the EN pin goes high, indicating
board removal, the GATE turns off immediately (with a 1mA
current to ground) and clears the board present bit, C4. If
the EN pin is pulled low, indicating a board insertion, all
fault bits except D4 are cleared and enable bit, C4, is set.
If the EN pin remains low for 100ms the state of the ON
pin is captured in ‘FET On’ control bit A3. This turns the
switch on if the ON pin is tied high. There is an internal
10μA pull-up current source on the EN pin.
If the system shuts down due to a fault, it may be desirable
to restart the system simply by removing and reinserting
a load card. In cases where the LTC4215-1/LTC4215-3 and
the switch reside on a backplane or midplane and the load
resides on a plug-in card, the EN pin detects when the
plug-in card is removed. Figure 4 shows an example where
the EN pin is used to detect insertion. Once the plug-in
card is reinserted the fault register is cleared (except for
D4). After 100ms the state of the ON pin is latched into
bit A3 of the control register. At this point the system
starts up again.
If a connection sense on the plug-in card is driving the EN
pin, insertion or removal of the card may cause the pin
voltage to bounce. This results in clearing the fault register
when the card is removed. The pin may be debounced
using a lter capacitor, CEN, on the EN pin as shown in
Figure 4. The lter time is given by:
tFILTER = CEN 123 [ms/μF]
FET Short Fault
A FET short fault is reported if the data converter mea-
sures a current sense voltage greater than or equal to
1.6mV while the GATE is turned off. This condition sets
FET short fault bit D5.
Power Bad Fault
A power bad fault is reported if the FB pin voltage drops
below its 1.235V threshold for more than 2μs when the
GATE is high. This pulls the GPIO1 pin low immediately
when congured as power-good, and sets power-bad pres-
ent bit, C3, and power bad fault bit D3. A circuit prevents
power-bad faults if the GATE-to-SOURCE voltage is low,
eliminating false power-bad faults during power-up or
power-down. If the FB pin voltage subsequently rises back
above the threshold, a power-good congured GPIO1 pin
returns to a high impedance state and bit C3 is reset.
Fault Alerts
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B has been set. This allows only selected
faults to generate alerts. At power-up the default state is
to not alert on faults and the GPIO2 pin is high. If an alert
is enabled, the corresponding fault causes the GPIO2 pin
to pull low. After the bus master controller broadcasts
the Alert Response Address, the LTC4215-1/LTC4215-3
respond with their addresses on the SDA line and releases
GPIO2 as shown in Table 6. If there is a collision between
two LTC4215-1/LTC4215-3s responding with their ad-
dresses simultaneously, then the device with the lower
address wins arbitration and responds rst. The GPIO2
line is also released if the device is addressed by the bus
master if GPIO2 is pulled low due to an alert.
Figure 4. Plug-In Card Insertion/Removal
APPLICATIONS INFORMATION
–
+
1.235V
GND
MOTHERBOARD
CONNECTOR
PLUG-IN
CARD
SOURCE
OUT
LTC4215-1
EN
CEN
LOAD
4215 F04
10μA
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