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參數(shù)資料
| 型號： | LTC4215CUFD-3#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-24 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 307K |
| 代理商： | LTC4215CUFD-3#TRPBF |
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LTC4215-1/LTC4215-3
16
421513fc
Once the GPIO2 signal has been released for one fault, it
is not pulled low again until the FAULT register indicates a
different fault has occurred or the original fault is cleared
and it occurs again. Note that this means repeated or con-
tinuing faults do not generate alerts until the associated
FAULT register bit has been cleared.
The GPIO2 pin may also be used as a general purpose
output by setting or resetting bit D6. When D6 is set,
GPIO2 will pull low, and when D6 is reset (default) GPIO2
will be high or pulled low due to an alert. The LTC4215-1/
LTC4215-3 will not respond to the alert response address
if the GPIO2 pin is being pulled low due to bit D6 being
set. See Figure 12 for a schematic detailing the behavior
of the GPIO2 pin.
Resetting Faults
Faults are reset with any of the following conditions. First,
a serial bus command writing zeros to the FAULT register
D bits 0-5 clears the associated faults. Second, FAULT
register bits 0-5 are cleared when the switch is turned
off by the ON pin or bit A3 going from high to low, if the
UV pin is brought below its 0.4V reset threshold for 2μs,
or if INTVCC falls below its 2.64V undervoltage lockout
threshold. Finally, when EN is brought from high to low,
only FAULT bits D0-D3 and D5 are cleared, and bit D4,
which indicates a EN change of state, is set. Note that faults
that are still present, as indicated in STATUS Register C,
cannot be cleared.
The FAULT register is not cleared when auto-retrying.
When auto-retry is disabled the existence of a D0, D1
or D2 fault keeps the switch off. As soon as the fault is
cleared, the switch turns on. If auto-retry is enabled, then
a high value in C0 or C1 holds the switch off and the fault
register is ignored. Subsequently, when bits C0 and C1
are cleared by removal of the fault condition, the switch is
allowed to turn on again. The LTC4215-1/LTC4215-3 will
set bit D2 and turn off in the event of an overcurrent fault,
preventing it from remaining in an overcurrent condition.
If congured to auto-retry, the LTC4215-1/LTC4215-3
will continually attempt to restart after cool-down cycles
until it succeeds in starting up without generating an
overcurrent fault.
Data Converter
The LTC4215-1/LTC4215-3 incorporate an 8-bit
ΔΣ A/D
converter that continuously monitors three different volt-
ages. The
ΔΣarchitectureinherentlyaveragessignalnoise
during the measurement period. The SOURCE pin has a
1/12.5 resistive divider to monitor a full scale voltage of
15.4V with 60mV resolution. The ADIN pin is monitored
with a 1.235V full scale and 4.82mV resolution, and the
voltage between the VDD and SENSE pins is monitored
with a 38.6mV full scale and 151μV resolution.
Results from each conversion are stored in registers E
(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,
and are updated 10 times per second. Setting CONTROL
register bit A5 invokes a test mode that halts the data
converter so that registers E, F, and G may be written to
and read from for software testing.
Conguring the GPIO Pins
Table 2 describes the possible states of the GPIO1 pin
using the control register bits A6 and A7. At power-up, the
default state is for the GPIO1 pin to be a general purpose
output with output value set by bit B6 (default 1 = GPIO1
Hi-Z). Other applications for the GPIO1 pin are to go high
impedance when power is good (FB pin greater than
1.235V), pull down when power is good, and a general
purpose input. Digital input information can be read from
bit C6 (Table 4).
Table 3 is used to congure the GPIO2 pin as a fault
alert output (See Fault Alerts) and also can be used as a
general purpose output and a general purpose input. By
default the GPIO2 pin is a general purpose output in the
high-impedance state as set by bit D6 (default 0 = GPIO2
Hi-Z, Table 5). Digital input information can be read from
bit C5 (Table 4).
The GPIO3 pin is a general purpose output/input that
defaults to output-low as set by bit D7 (default 1 = GPIO3
pulled low, Table 5). Digital input information can be read
from bit C2 (Table 4).
APPLICATIONS INFORMATION
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| LTC4215CUFD-3 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| LTC4215IUFD-3#PBF | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| LTC4222CG#PBF | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36 |
| LTC4222CG#TRPBF | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36 |
| LTC4222IUH#TRPBF | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
相關代理商/技術參數(shù) |
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| LTC4215IGN | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Hot Swap Controller with I2C Compatible Monitoring |
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| LTC4215IUFD | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Hot Swap Controller with I2C Compatible Monitoring |
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