參數(shù)資料
型號： LTC4211IMS8
廠商： Linear Technology
文件頁數(shù)： 16/40頁
文件大小： 321K
描述： IC CONTROLLER HOT SWAP 8-MSOP
標(biāo)準(zhǔn)包裝： 50
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無
電源電壓： 2.5 V ~ 16.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
LTC4211
16
4211fb
OPERATION
a start-up check to make sure the supply voltage is above
its 2.3V UVLO threshold (see Time Point 1). If the input
supply voltage is valid, the gate of the external pass tran-
sistor is pulled to ground by the internal 200糀 current
source connected at the GATE pin. The TIMER pin is held
low by an internal N-channel pull-down transistor (see
M6, LTC4211 Block Diagram) and the FILTER pin voltage
is pulled to ground by an internal 10糀 current source.
Once V
CC
 and ON (the ON pin is >1.316) are valid, the
LTC4211 checks to make sure that GATE is OFF (V
GATE
 <
0.2V) at Time Point 2. An internal timing circuit is enabled
and the TIMER pin voltage ramps up at the rate described by
Equation 1. At Time Point 3 (the timing period programmed
by C
TIMER
), the TIMER pin voltage equals V
TMR
 (1.236V).
Next, the TIMER pin voltage ramps down to Time Point 4
where the LTC4211 performs two checks: (1) FILTER pin
voltage is low (V
FILTER
 < 1.156V) and (2) FAULT pin volt-
age is high (V
FAULT
 > 1.286V). If both conditions are met,
the LTC4211 begins a second timing (soft-start) cycle.
Second Timing (Soft-Start) Cycle
At the beginning of the second timing cycle (Time Point?),
the LTC4211s FAST COMP is armed and an internal 10糀
current source working with an internal charge pump
provides the gate drive to the external pass transistor. The
LTC4211 automatically limits the inrush current in one of
two ways: by controlling the GATE pin voltage slew rate
or by actively limiting the inrush current. If GATE voltage
slew rate control is preferred, an external capacitor C
GATE
 
can be used from GATE to ground, as shown in Figure 6.
An expression for the GATE voltage slew rate is given by
Equation 3:
 
GATE
SlewRate,
dV
GATE
dt
=
10礎(chǔ)
C
 
(3)
Adding C
GATE
 slows the GATE voltage slew rate at the ex-
pense of slower system turn-on and turn-off time. Should
this technique be used, values for C
GATE
 less than 150nF
are recommended.
The inrush current being delivered to the load while
the GATE is ramping is dependent on C
LOAD
 and C
GATE
.
Equation 4 gives an expression for the inrush current
during the second timing cycle:
 
INRUSH
=
dV
GATE
dt
"C
LOAD
=10礎(chǔ) "
C
LOAD
C
ATE
 
(4)
For example, if C
GATE
 = 3300pF and C
LOAD
 = 2000糉, the
inrush current charging C
LOAD
 is:
 
INRUSH
=10礎(chǔ)"
2000礔
0.0033 F
= 6.06A
 
(5)
At Time Point 6, the output voltage trips COMP2s thresh-
old, signaling an output voltage power good condition.
At Time Point 7, RESET is asserted high, SLOW COMP is
armed and the LTC4211 enters a fault monitor mode. The
TIMER voltage then ramps down to Time Point 8.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
ON
 < 1.236V). The GATE pin
voltage is ramped to ground by the internal 200糀 cur-
rent source, discharging C
GATE
 and turning off the pass
transistor. As C
LOAD
 discharges, the output voltage crosses
COMP2s threshold, signaling a power bad condition at
Time Point 10. At this point, RESET is asserted low.
Figure 6. Using an External Capacitor at GATE for
GATE Voltage Slew Rate Control
M1
Si4410DY
R
SENSE
0.007?/DIV>
C
GATE
*
C
LOAD
4211 F06
+
V
CC
SENSE
LTC4211**
GATE
FB
R1
36k
V
OUT
5V
5A
V
IN
5V
R2
15k
*
**
VALUES d150nF SUGGESTED
ADDITIONAL DETAILS OMITTED
FOR CLARITY
=
dV
GATE
dt
V
GATE
 SLEW RATE CONTROL
10糀
C
GATE
(
)
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