
LTC4099
4099fd
throughILIM0intheI2Cportdeterminewhetherthesus-
pendLDOwilllimitinputcurrenttothelowpowersetting
of500Aorthehighpowersettingof2.5mA.
Interrupt Generation
TheIRQpinontheLTC4099isanopen-drainoutputthat
canbeusedtogenerateaninterruptbasedononeormore
of a multitude of maskable PowerPath/battery charger
change events. The interrupt mask register column in
Table1indicatesthecategoriesofeventsthatcangener-
ateaninterrupt.Ifa1iswrittentoagivenlocationinthe
maskregister,thenanychangeinthestatusdataofthat
categorywillcauseaninterrupttooccur.Forexample,if
a1iswrittentobit6ofthemaskregister,thenaninter-
ruptwillbegeneratedwhentheWALLUVLOdetectsthat
eitherpowerhasbecomeavailableatWALL,orthatpower
wasavailableandisnolongeravailablefromWALL.Ifa
1iswrittentobit2ofthemaskregister,thenaninterrupt
willbetriggeredbyanychangeinthestatusbitsofthe
batterycharger,asgivenbyTable8.Likewise,a1atbit3
willallowaninterruptduetoanychangeinthethermistor
statusbitsofTable7.
TheIRQpinisclearedwhenthebusmasteracknowledges
receiptofstatusdatafromareadoperation.Ifthemaster
doesnotacknowledgethestatusbyte,theinterruptwill
notbeclearedandtheIRQpinwillnotbereleased.
Upongenerationofaninterrupt,thecurrentstateofthe
LTC4099 is recorded in the I2C port for retrieval (see
OutputData).
I2C Interface
TheLTC4099maycommunicatewithabusmasterusing
thestandardI2C2-wireinterface.TheTimingDiagram
showstherelationshipofthesignalsonthebus.Thetwo
buslines,SDAandSCL,mustbeHIGHwhenthebusis
notinuse.Externalpull-upresistorsorcurrentsources,
such as the LTC1694 SMBus accelerator, are required
ontheselines.TheLTC4099isbothaslavereceiverand
slavetransmitter.TheI2Ccontrolsignals,SDAandSCL,
arescaledinternallytotheDVCCsupply.DVCCshouldbe
connectedtothesamepowersupplyasthebuspull-up
resistors.
TheI2CporthasanundervoltagelockoutontheDVCCpin.
WhenDVCCisbelowapproximately1V,theI2Cserialport
iscleared,theLTC4099issettoitsdefaultconfiguration
ofallzerosandinterruptswillbelockedout.
Bus Speed
TheI2Cportisdesignedtobeoperatedatspeedsofup
to400kHz.Ithasbuilt-intimingdelaystoensurecorrect
operationwhenaddressedfromanI2Ccompliantmaster
device.Italsocontainsinputfiltersdesignedtosuppress
glitchesshouldthebusbecomecorrupted.
START and STOP Conditions
Abusmastersignalsthebeginningofcommunications
bytransmittingaSTARTcondition.ASTARTconditionis
generatedbytransitioningSDAfromHIGHtoLOWwhile
SCLisHIGH.Themastermaytransmiteithertheslave
writeortheslavereadaddress.Oncedataiswrittentothe
LTC4099,themastermaytransmitaSTOPconditionwhich
commandstheLTC4099toactuponitsnewcommandset.
ASTOPconditionissentbythemasterbytransitioning
SDAfromLOWtoHIGHwhileSCLisHIGH.
Byte Format
Eachbytesentto,orreceivedfrom,theLTC4099must
beeightbitslongfollowedbyanextraclockcycleforthe
acknowledgebit.ThedatashouldbesenttotheLTC4099
mostsignificantbit(MSB)first.
Acknowledge
Theacknowledgesignalisusedforhandshakingbetween
themasterandtheslave.WhentheLTC4099iswritten
to(writeaddress),itacknowledgesitswriteaddressas
wellasthesubsequenttwodatabytes.Whenitisread
from(readaddress),theLTC4099acknowledgesitsread
addressonly.Thebusmastershouldacknowledgereceipt
ofinformationfromtheLTC4099.
Anacknowledge(activeLOW)generatedbytheLTC4099
letsthemasterknowthatthelatestbyteofinformationwas
received.Theacknowledgerelatedclockpulseisgenerated
bythemaster.ThemasterreleasestheSDAline(HIGH)
duringtheacknowledgeclockcycle.TheLTC4099pulls
operaTion