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參數(shù)資料
| 型號(hào)： | LTC4095EDC#TRM |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 2 X 2 MM, 0.75 MM HEIGHT, PLASTIC, DFN-8 |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | LTC4095EDC#TRM |
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LTC4095
9
4095fa
OPERATION
In any mode, the actual battery current can be determined
by monitoring the PROG pin voltage and using the follow-
ing equation:
I
PROG
R
BAT
PROG
=
800
Thermal Regulation
To prevent thermal damage to the IC or surrounding
components, an internal thermal feedback loop will
automatically decrease the programmed charge current
if the die temperature rises to approximately 115°C.
Thermal regulation protects the LTC4095 from excessive
temperature due to high power operation or high ambient
thermal conditions and allows the user to push the limits
of the power handling capability with a given circuit board
design without risk of damaging the LTC4095 or external
components. The benet of the LTC4095 thermal regula-
tion loop is that charge current can be set according to
actual conditions rather than worst-case conditions with
the assurance that the battery charger will automatically
reduce the current in worst-case conditions.
Charge Status Indication
The CHRG pin indicates the status of the battery charger.
Four possible states are represented by CHRG: charging,
not charging, unresponsive battery and battery temperature
out of range.
The signal at the CHRG pin can be easily recognized as one
of the above four states by either a human or a micropro-
cessor. The CHRG pin, which is an open-drain output, can
drive an indicator LED through a current limiting resistor
for human interfacing, or simply a pull-up resistor for
microprocessor interfacing.
To make the CHRG pin easily recognized by both humans
and microprocessors, the pin is either a DC signal of
ON for charging, OFF for not charging, or it is switched
at high frequency (35kHz) to indicate the two possible
faults: unresponsive battery and battery temperature out
of range.
When charging begins, CHRG is pulled low and remains
low for the duration of a normal charge cycle. When the
charge current has dropped to below 10% of the full-scale
current, the CHRG pin is released (high impedance). If a
fault occurs after the CHRG pin is released, the pin re-
mains high impedance. However, if a fault occurs before
the CHRG pin is released, the pin is switched at 35kHz.
While switching, its duty cycle is modulated between a high
and low value at a very low frequency. The low and high
duty cycles are disparate enough to make an LED appear
to be on or off thus giving the appearance of “blinking”.
Each of the two faults has its own unique “blink” rate for
human recognition as well as two unique duty cycles for
microprocessor recognition.
Table 1 illustrates the four possible states of the CHRG
pin when the battery charger is active.
Table 1. CHRG Output Pin
STATUS
FREQUENCY
MODULATION
(BLINK)
FREQUENCY
DUTY CYCLE
Charging
0Hz
0 Hz (Lo-Z)
100%
IBAT < C/10
0Hz
0 Hz (Hi-Z)
0%
NTC Fault
35kHz
1.5Hz at 50%
6.25% to 93.75%
Bad Battery
35kHz
6.1Hz at 50%
12.5% to 87.5%
An NTC fault is represented by a 35kHz pulse train whose
duty cycle varies between 6.25% and 93.75% at a 1.5Hz
rate. A human will easily recognize the 1.5Hz rate as a
“slow” blinking which indicates the out of range battery
temperature while a microprocessor will be able to decode
either the 6.25% or 93.75% duty cycles as an NTC fault.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below VTRKL for over 1/2 hour), the
CHRG pin gives the battery fault indication. For this fault,
a human would easily recognize the frantic 6.1Hz “fast”
blinking of the LED while a microprocessor would be able
to decode either the 12.5% or 87.5% duty cycles as a bad
battery fault.
Although very improbable, it is possible that a duty cycle
reading could be taken at the bright-dim transition (low
duty cycle to high duty cycle). When this happens the
duty cycle reading will be precisely 50%. If the duty cycle
reading is 50%, system software should disqualify it and
take a new duty cycle reading.
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