參數(shù)資料
型號(hào)： LTC4012IUF#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 633 kHz SWITCHING FREQ-MAX, PQCC20
封裝： 4 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-220WGGD-1, QFN-20
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 381K
代理商： LTC4012IUF#PBF
LTC4012/
LTC4012-1/LTC4012-2
4012fa
Figure 12. High Speed Switching Path
4012 F12
VBAT
L1
RSENSE
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
ANALOG
GROUND
SYSTEM
GROUND
SWITCH NODE
CIN
SWITCHING GROUND
COUT
VIN
GND
D1
+
The LTC4012 can be soft-started with the compensation
capacitor on the ITH pin. At start-up, ITH will quickly rise
to about 0.25V, then ramp up at a rate set by the com-
pensation capacitor and the 40A ITH bias current. The
full programmed charge current will be reached when ITH
reaches approximately 2V. With a 0.1F capacitor, the time
to reach full charge current is usually greater than 1.5ms.
This capacitor can be increased if longer start-up times
are required, but loop bandwidth and dynamic response
will be reduced.
INTVDD Regulator Output
Bypass the INTVDD regulator output to GND with a low
ESR X5R or X7R ceramic capacitor with a value of 0.47F
or larger. The capacitor used to build the BOOST supply
(C2 in Figure 11) can serve as this bypass. Do not draw
more than 30mA from this regulator for the host system,
governed by IC power dissipation.
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperatureisnotexceededunderalloperatingconditions.
The thermal resistance of the LTC4012 package (
θJA) is
37°C/W, provided the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
applicationwilldependonforcedaircoolingandotherheat
sinkingmeans,especiallytheamountofcopperonthePCB
to which the LTC4012 is attached. The following formula
may be used to estimate the maximum average power dis-
sipation PD (in watts) of the LTC4012, which is dependent
upon the gate charge of the external MOSFETs. This gate
charge, which is a function of both gate and drain voltage
swings, is determined from specifications or graphs in the
manufacturer’s data sheet. For the equation below, find the
gatechargeforeachtransistorassuming5Vgateswingand
a drain voltage swing equal to the maximum VCLP voltage.
Maximum LTC4012 power dissipation under normal op-
erating conditions is then given by:
PD = DCIN(3mA + IDD + 665kHz(QTGATE + QBGATE))
– 5IDD
applications inForMation
where:
IDD = Average external INTVDD load current, if any
QTGATE = Gate charge of external top FET in Coulombs
QBGATE = Gate charge of external bottom FET in
Coulombs
PCB Layout Considerations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4012 is essential. Refer
to Figure 12. For maximum efficiency, the switch node
rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4012 close to the switching FET gate
terminals, keeping the connecting traces short to
producecleandrivesignals.ThisrulealsoappliestoIC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
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