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參數(shù)資料
| 型號： | LTC3890EGN-1#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO28 |
| 封裝： | LEAD FREE, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 498K |
| 代理商： | LTC3890EGN-1#PBF |
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LTC3890-1
26
38901f
APPLICATIONS INFORMATION
Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V (max), VOUT = 3.3V, IMAX = 5A,
VSENSE(MAX) = 75mV and f = 350kHz.
The inductance value is chosen rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
IL =
VOUT
f
() L
( )
1– VOUT
VIN(NOM)
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum VIN:
t
V
Vf
V
VkHz
ns
ON MIN
OUT
IN MAX
()
.
=
()
=
()
=
33
22
350
429
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (43mV):
RSENSE ≤
64mV
5.73A
≈ 0.01Ω
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
PMAIN =
3.3V
22V
5A
()
2 1+ 0.005
() 50°C– 25°C
()
0.035
()+ 22V
()
2
5A
2
2.5
() 215pF
()
1
5V – 2.3V
+
1
2.3V
350kHz
() = 331mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC =
34mV
0.01
– 1
2
95ns 22V
()
4.7μH
=
3.18A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = 3.18A
()
2
1.125
() 0.022Ω
()
= 250mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (ΔIL) = 0.02Ω(1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
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