參數(shù)資料
型號(hào): LTC3851AIUD-1#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: 0.05 A SWITCHING CONTROLLER, 810 kHz SWITCHING FREQ-MAX, PQCC16
封裝: 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16
文件頁(yè)數(shù): 4/30頁(yè)
文件大?。?/td> 0K
代理商: LTC3851AIUD-1#TRPBF
LTC3851A-1
12
3851a1fa
operaTion
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator,
IREV, turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as in
normal operation. In this mode the efficiency at light loads
is lower than in Burst Mode operation. However, continu-
ous mode has the advantages of lower output ripple and
less interference to audio circuitry.
When the MODE/PLLIN pin is connected to GND, the
LTC3851A-1 operates in PWM pulse-skipping mode at
light loads. At very light loads the current comparator,
ICMP, may remain tripped for several cycles and force the
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
likeforcedcontinuousoperation,exhibitslowoutputripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency of
the LTC3851A-1 can be selected using the FREQ/PLLFLTR
pin. If the MODE/PLLIN pin is not being driven by an ex-
ternal clock source, the FREQ/PLLFLTR pin can be used
to program the controller’s operating frequency from
250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3851A-1
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controlleroperatesinforcedcontinuousmodeofoperation
when it is synchronized. A series RC should be connected
between the FREQ/PLLFLTR pin and GND to serve as the
PLL’s loop filter.
It is suggested that the external clock be applied before
enabling the controller unless a second resistor is con-
nected in parallel with the series RC loop filter network.
The second resistor prevents low switching frequency
operation if the controller is enabled before the clock.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is
also pulled low when the RUN pin is low (shut down) or
whentheLTC3851A-1isinthesoft-startortrackingphase.
When the VFB pin voltage is within the ±10% requirement,
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source of up to 6V.
The PGOOD pin will flag power good immediately when
the VFB pin is within the ±10% window. However, there is
an internal 17s power bad mask when VFB goes out of
the ±10% window.
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