參數(shù)資料
型號: LTC3827IG-1#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3 A DUAL SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 5.30 MM, PLASTIC, SSOP-28
文件頁數(shù): 7/32頁
文件大?。?/td> 448K
代理商: LTC3827IG-1#TR
LTC3827-1
15
38271fe
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
VOUT
VIN
IMAX
()2 1+
()R
DS(ON) +
VIN
()2 IMAX
2
RDR
() C
MILLER
()
1
VINTVCC –VTHMIN
+
1
VTHMIN
f
()
PSYNC =
VIN –VOUT
VIN
IMAX
()2 1+
()R
DS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efciency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON)device
with lower CMILLER actually provides higher efciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in
Figure 14 conduct during the dead-time between the
conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a re-
verse recovery period that could cost as much as 3% in
efciency at high VIN. A 1A to 3A Schottky is generally a
good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
CIN and COUT Selection
The selection of CIN is simplied by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phase technique typically reduces the input capacitor’s RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS
IMAX
VIN
VOUT
() V
IN –VOUT
() 1/2
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even signicant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3827-1, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benet of the LTC3827-1 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the dual
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