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參數(shù)資料
| 型號： | LTC3806EDE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Flyback DC/DC Controller |
| 中文描述： | 0.05 A SWITCHING CONTROLLER, 290 kHz SWITCHING FREQ-MAX, PDSO12 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 241K |
| 代理商： | LTC3806EDE |
15
LTC3806
3806f
APPLICATIOU
Continuing our previous example the filter capacitor for
output 1 needs:
W
U
U
ESR
V
A
m
C
A
V
kHz
F
COUT
OUT
≤
(
)
=
≥
=
μ
0 01 3 3
.
1 0 579
– .
2
7
2
0 01 3 3
.
250
242
.
.
To get an electrolytic capcitor with an ESR this low would
require C
OUT
much larger than 242
μ
F. Combining a low
ESR ceramic capacitor in parallel with an electrolytic
capacitor provides better filtering at lower cost.
For output 2, the output capacitor needs an ESR less than
42m
and a bulk C greater than 40.4
μ
F. This can be
achieved with a single high performance capacitor such as
a Sanyo OS-CON or equivalent.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board. Parasitic
inductance from poor layout can have a significant impact
on ripple. Refer to the layout section for details.
Power MOSFET Selection
Important selection criteria for the power MOSFETs in-
clude the “on” resistance R
DS(ON)
, input capacitance,
drain-to-source breakdown voltage (BV
DSS
) and maxi-
mum drain current (I
D(MAX)
).
Narrow the choices for power MOSFETs by first looking at
the maximum drain currents. For the primary-side power
MOSFET:
P
V
D
IN MIN
MAX
(
I
X
PK
IN
)
MIN
2
=
+
1
For each secondary-side power MOSFET:
I
I
D
X
PK
OUT
MAX
MIN
2
=
+
1
1
–
From the remaining MOSFET choices, narrow the field
based on BV
DSS
. Select a primary-side power MOSFET
with a BV
DSS
greater than:
BV
I
L
C
V
V
N
DSS
PK
LKG
P
IN MAX
(
OUT MAX
(
≥
+
+
)
)
where L
LKG
is the primary-side leakage inductance and C
P
is the primary-side capacitance (mostly from the C
OSS
of
the primary-side power MOSFET). A snubber may be
added to reduce the leakage inductance related spike. For
more information on snubber design, refer to Application
Note 19.
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
≥
V
OUT
+ V
IN(MAX)
N
Next, select a logic-level MOSFET with acceptable R
DS(ON)
at the nominal gate drive voltage (usually 6.9V—set by the
INTV
CC
regulator).
Calculate the required RMS currents next. For the primary-
side power MOSFET:
I
P
)
V
D
RMSPRI
IN
IN MIN
(
MAX
=
For each secondary-side power MOSFET:
I
I
D
RMSSEC
OUT
MAX
=
1
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
DS
, a term
for transition power loss must be included in order to get
an accurate fix on power dissipation. C
MILLER
is the most
critical parameter in determining the transition loss but is
not directly specified on MOSFET data sheets.
C
MILLER
can be calculated from the gate charge curve in-
cluded on most data sheets (Figure 6). The curve is gen-
erated by forcing a constant input current into the gate of
a common source, current source loaded stage and then
plotting the gate voltage versus time. The initial slope is the
result of the gate-to-source and the gate-to-drain capaci-
tance. The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops. The
upper sloping line is due to the gate-to-drain accumulation
capacitance and the gate-to-source capacitance. The Miller
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