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參數(shù)資料
| 型號： | LTC3772ETS8#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 1 MM HEIGHT, PLASTIC, MO-193, SOT-23, 8 PIN |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 248K |
| 代理商： | LTC3772ETS8#PBF |
14
LTC3772
3772f
APPLICATIO S I FOR ATIO
WU
UU
To prevent excessive heating in the diode, foldback current
limiting can be added to reduce the current in proportion
to the severity of the fault.
Foldback current limiting is implemented by adding diodes
DFB1 and DFB2 between the output and the ITH/RUN pin as
shown in Figure 4. In a hard short (VOUT = 0V), the current
will be reduced to approximately 50% of the maximum
output current.
Figure 4. Foldback Current Limiting
VFB
ITH/RUN
VOUT
LTC3772
RA
3772 F04
RB
DFB1
DFB2
and values determine the loop feedback factor gain and
phase. An output current pulse of 20% to 100% of full load
current having a rise time of 1s to 10s will produce
output voltage and ITH pin waveforms that will give a sense
of the overall loop stability. The gain of the loop will be
increased by increasing RC, and the bandwidth of the loop
will be increased by decreasing CC. The output voltage
settling behavior is related to the stability of the closed-
loop system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10F capacitor would require a 250s rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC3772 is capable of turning the top
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3772 is
about 250ns. Low duty cycle and high frequency applica-
tions may approach this minimum on-time limit and care
should be taken to ensure that:
t
V
fV
ON MIN
OUT
IN
()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3772 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ILOAD also begins to charge or dis-
charge COUT, which generates a feedback error signal. The
regulator loop then returns VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for over-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Figure 5 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggested values) to optimize transient response once the
final PC layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be decided upon because the various types
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