參數(shù)資料
型號: LTC3728LIGN-1
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3 A DUAL SWITCHING CONTROLLER, 590 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.150 INCH, PLASTIC, SSOP-28
文件頁數(shù): 16/32頁
文件大?。?/td> 475K
代理商: LTC3728LIGN-1
LTC3728L-1
23
3728l1fc
APPLICATIONS INFORMATION
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from INTVCC
to ground. The resulting dQ/dt is a current out of INTVCC
that is typically much larger than the control circuit cur-
rent. In continuous mode, IGATECHG =f(QT+QB), where QT
and QB are the gate charges of the topside and bottom
side MOSFETs.
Supplying INTVCC power through the EXTVCC switch input
from an output-derived source will scale the VIN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efciency). For example, in a 20V to 5V ap-
plication, 10mA of INTVCC current results in approximately
2.5mA of VIN current. This reduces the mid-current loss
from 10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current ows through L and
RSENSE, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resistances
of L, RSENSE and ESR to obtain I2R losses. For example, if
each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and
RESR = 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results
in losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efciency varies as the inverse
square of VOUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signicant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss =
VIN
()2 IMAX
2
RDR
()
CMILLER
() f()
1
5V – VTH
+
1
VTH
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efciency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has ad-
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20μF to 40μF of capacitance having a maximum of 20mΩ
to 50mΩ of ESR. The LTC3728L-1 2-phase architecture
typically halves this input capacitance requirement over
competing solutions. Other losses including Schottky con-
duction losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by
an amount equal to ΔILOAD (ESR), where ESR is the ef-
fective series resistance of COUT. ΔILOAD also begins to
charge or discharge COUT generating the feedback error
signal that forces the regulator to adapt to the current
change and return VOUT to its steady-state value. During
this recovery time VOUT can be monitored for excessive
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values.
The availability of the ITH pin
not only allows optimization of control loop behavior but
also provides a DC coupled and AC ltered closed loop
response test point. The DC step, rise time and settling
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