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參數(shù)資料
| 型號(hào)： | LTC3625EDE#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封裝： | 3 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 262K |
| 代理商： | LTC3625EDE#TRPBF |
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LTC3625/LTC3625-1
0
3625f
operaTion
converter will turn off. Once VMID has again risen above
the VMID(GOOD) threshold, the boost converter will be
re-enabled. In the case where VOUT < VMID, the boost
converter will operate in trickle charge mode until VOUT
exceeds VMID (see Boost Converter).
3. During phase 2, if CBOT exceeds its individual maximum
threshold voltage (2.45V/2.05V typical if VSEL is low
or 2.7V/2.3V typical if VSEL is high) or if VTOP exceeds
VBOT by more than 50mV (typical), then the appropri-
ate converter will turn off until the capacitor has fallen
below its hysteresis threshold (2.40V/2V typical if VSEL
is low and 2.65V/2.25V typical if VSEL is high for the
buck converter or VTOP < VMID – 50mV typical for the
boost converter).
4. Once VOUT has reached its programmed output voltage,
the part will enter sleep mode, and only minimal power
will be consumed (see the Electrical Characteristics
table).
5. If the supercapacitors’ self discharge or an external load
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin recharging the supercapacitor stack.
In all cases, whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
Charge time is dependent on the programmed buck out-
put current as well as the value of supercapacitors being
charged.Forestimatingchargeprofilesinthedualinductor
application, see the Typical Performance Characteristics
graph Charge Time vs RPROG.
The effective average VOUT referred charge current, while
both converters are continuously active, can be approxi-
mated as:
I
A
V
CHARGE
BUCK
BOOST
MID
OUT
0 5
1
1 2
.
–
–
ε
And, while both supercapacitors are in balance and VMID
is above the VMID(GOOD) threshold as:
ICHARGE 0.5 IBUCK εBOOST
where
εBOOST is the boost converter efficiency which is
typically around 85% (see the Typical Performance Char-
acteristics graph Boost Efficiency vs VTOP).
Seen another way this is the maximum steady-state load
the part can support without losing VOUT regulation.
PGOOD PIN
The PGOOD pin is an open-drain output used to indicate
thatVOUThasapproacheditsfinalregulationvalue.PGOOD
remains active low until VOUT reaches 92.5% of its regula-
tion value at which point it will become high impedance.
If VOUT falls below 89.5% of its regulation voltage after
PGOOD has been asserted, PGOOD will once again pull
active low. PGOOD is an open-drain output and requires
a pull-up resistor to the input voltage of the monitoring
microprocessor or another appropriate power source.
PGOOD is pulled active low in shutdown or input UVLO.
Power-Fail Input Comparator
The PFI/PFO pins provide an input failure notification to
the user. The PFI pin is a high impedance input pin that
should be tied to a resistive divider from VIN. PFO is an
open-drain output and requires a pull-up resistor to the
inputvoltageofthemonitoringmicroprocessororanother
appropriate power source. When PFI is above 1.2V, PFO is
high impedance and will be pulled up through the external
resistor. If PFI drops below 1.2V, PFO will be pulled low
indicating a power failure. This allows the user to program
any desired input power failure indication threshold. There
is 15mV of hysteresis on the PFI pin. If this functionality
is not desired the PFI pin should be tied to VIN. PFO is
pulled active low in shutdown or input UVLO
Shutdown Operation
When the EN pin is pulled low the LTC3625/LTC3625-1 are
put into shutdown. In this case, all of the active circuitry is
powered down and there will be less than 1A of leakage
current from both VIN and VOUT. This allows the input to
be present or absent as well as the capacitor stacks to be
fully charged or discharged in shutdown without leakage
between VIN, VOUT and GND.
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