參數(shù)資料
型號: LTC3568IDD
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 4 A SWITCHING REGULATOR, 4000 kHz SWITCHING FREQ-MAX, PDSO10
封裝: 3 X 3 MM, PLASTIC, MO-229WEED-2, DFN-10
文件頁數(shù): 3/18頁
文件大?。?/td> 300K
代理商: LTC3568IDD
LTC3568
3568fa
RUN
RT
SHDN/RT
(3a)
(3b)
(3c)
RUN
RT
SHDN/RT
1M
SVIN
3568 F03
RUN OR VIN
ITH
C1
CC
D1
RC
R1
applicaTions inForMaTion
internal digital soft-start which steps up a clamp on ITH
over 1024 clock cycles, as can be seen in Figure 4.
The soft-start time can be increased by ramping the volt-
age on ITH during start-up as shown in Figure 3(c). As
the voltage on ITH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
to ground, pulse skipping operation is selected which
provides the lowest output voltage and current ripple
at the cost of low current efficiency. Applying a voltage
between SVIN – 1V and 1V, results in forced continuous
mode, which creates a fixed output ripple and is capable
of sinking some current (about 1/2
ΔIL). Since the switch-
ing noise is constant in this mode, it is also the easiest to
filter out. In many cases, the output voltage can be simply
connected to the SYNC/MODE pin, giving the forced con-
tinuous mode, except at startup.
The LTC3568 can also be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the rising
edge of the external clock.
CheckingTransientResponse
The OPTI-LOOP compensation allows the transient
response to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not only
allows optimization of the control loop behavior but also
providesaDC-coupledandACfilteredclosedloopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The ITH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1s
to 10s will produce output voltage and ITHpinwaveforms
Figure3.SHDN/RTPinInterfacingandExternalSoft-Start
Figure4.DigitalSoft-Start
VIN = 3.3V
VOUT = 2.5V
ILOAD = 1.8A
VIN
5V/DIV
VOUT
1V/DIV
IL
1A/DIV
400s/DIV
3568 F04
ModeSelectionandFrequencySynchronization
The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
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