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參數(shù)資料
| 型號： | LTC3553EUD#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 518K |
| 代理商： | LTC3553EUD#PBF |
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LTC3553
24
3553fa
OPERATION
(together with the buck regulator). When the STBY pin is
brought high, LDO bias current is reduced. Unlike the buck
regulator, the LDO’s load capability remains unchanged.
However, the LDO’s transient response is slowed, as il-
lustrated in Figure 5 and Figure 6.
sirable operation may occur. In applications where the
buck input is supplied from other than the VOUT pin, other
measures should be taken to ensure that the buck is not
operated outside the specied BVIN input supply range,
as operation beyond this range is not guaranteed.
LDO Regulator UVLO Considerations
The LDO regulator’s bias current is supplied via an internal
connection to the USB PowerPath VOUTpin.TheVOUTUVLO
shuts down the LDO when VOUT drops below about 2.6V
in order to prevent the LDO from operating incorrectly
due to too low a bias supply voltage.
The LDO power input pin, VINLDO, can be driven with as
little as 1.65V. There is, however, no UVLO to enforce
this requirement. It is thus recommended that VINLDO be
tied to either the buck regulator output (programmed to
regulate at least 1.65V), or to the USB PowerPath VOUT
pin, to ensure proper operation.
PUSHBUTTON INTERFACE
State Diagram/Operation
Figure 7 shows the LTC3553 pushbutton state diagram.
Upon rst application of power, VBUS or BAT, an inter-
nal power on reset (POR) signal places the pushbutton
circuitry into the power-down (PDN1) state. One second
Figure 7. Pushbutton State Diagram
3553 F07
PUP2
PDN1
PDN2
HRST
POR
UVLO AND
EITHER BUCK_ON
OR LDO_ON
BUCK_ON
OR LDO_ON
EXTPWR OR
PB400MS
1SEC
5SEC
1SEC
PON
PUP1
HR
UVLO OR
BOTH BUCK_ON
AND LDO_ON
EXTPWR OR
PB400MS
POFF
Figure 5. LDO Load Step Response in Normal Operation
LDO REGULATING 3.3V
4.7μF OUTPUT CAPACITOR
STBY LOW
LDO OUTPUT
VOLTAGE
AC-COUPLED
0.1V/DIV
150mA
5mA
ILDO
3553 F05
50μs/DIV
LDO REGULATING 3.3V
4.7μF OUTPUT CAPACITOR
STBY HIGH
LDO OUTPUT
VOLTAGE
AC-COUPLED
0.1V/DIV
150mA
5mA
3553 F06
50μs/DIV
ILDO
VOUT UNDERVOLTAGE LOCKOUT (VOUT UVLO)
An undervoltage lockout circuit on the USB PowerPath
VOUT pin shuts down and prevents both the buck and
the LDO from enabling when the VOUT pin voltage drops
below about 2.6V.
Buck Regulator UVLO Considerations
It is recommended that the buck regulator input supply
(BVIN pin) be connected directly to the USB PowerPath
output (VOUT pin). With this connection, the VOUT UVLO
prevents the buck regulator from operating at low input
supply voltages where loss of regulation or other unde-
Figure 6. LDO Load Step Response in Standby Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC3554 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators |
| LTC3554EPD | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators |
| LTC3554EPD#PBF | 功能描述:IC USB POWER MANAGER 20-UTQFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 標準包裝:1 系列:- 應用:手持/移動設備 電流 - 電源:- 電源電壓:3 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-LLP-EP（4x4） 包裝:Digi-Reel® 配用:LP3905SD-30EV-ND - BOARD EVALUATION LP3905SD-30 其它名稱:LP3905SD-30DKR |
| LTC3554EPD#TRPBF | 功能描述:IC USB POWER MANAGER 20-UTQFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:37 系列:- 應用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應商設備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| LTC3554EPDPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators |
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