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參數(shù)資料
| 型號： | LTC3549EDCB#TRM |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.6 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封裝： | 2 X 3 MM, 0.75 MM HEIGHT, PLASTIC, MO-229, DFN-6 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 352K |
| 代理商： | LTC3549EDCB#TRM |
LTC3549
13
3549f
APPLICATIO S I FOR ATIO
WU
U
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3549. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
1. Does the capacitor CIN connect to the power VIN (Pin 1)
and GND (Pins 2, 7) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
Figure 3a. Buck Regulator Top Layer
signals VFB should be routed away from noisy compo-
nents and traces, such as the SW line (Pin 3), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor CIN and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
CIN or COUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to VIN or GND.
Figure 3b. Buck Regulator Bottom Layer
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