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參數(shù)資料
| 型號： | LTC3547BEDDB |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.7 A DUAL SWITCHING CONTROLLER, 2700 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 3 X 2 MM, 0.75 MM HEIGHT, PLASTIC, M0-229WECD-1, DFN-8 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 270K |
| 代理商： | LTC3547BEDDB |
LTC3547B
12
3547bfa
APPLICATIO S I FOR ATIO
WU
U
Thermal Considerations
In a majority of applications, the LTC3547B does not dis-
sipate much heat due to its high efciency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
TRISE = PD θJA
(6)
Where PD is the power dissipated by the regulator and
θJA is the thermal resistance from the junction of the die
to the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
(7)
As a worst-case example, consider the case when the
LTC3547B is in dropout on both channels at an input
voltage of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the RDS(ON)
of the main switch is 0.9Ω. Therefore, power dissipated
by each channel is:
PD = IOUT2 RDS(ON) = 81mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547B device operating in a 70°C
ambient temperature is approximately:
TJ = (2 0.081W 76°C/W) + 70°C = 82.3°C
which is well below the absolute maximum junction tem-
perature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547B. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective COUT and L closely connected?
The (–) plate of COUT returns current to GND and the
(–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground sense line
terminated near GND (Pin 5). The feedback signals VFB1
and VFB2 should be routed away from noisy components
and traces, such as the SW lines (Pins 4 and 6), and
their trace length should be minimized.
4. Keep sensitive components away from the SW pins if
possible. The input capacitor CIN and the resistors R1,
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of CIN or COUT.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to VIN or GND.
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