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參數(shù)資料
| 型號： | LTC3542EDC |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封裝： | 2 X 2 MM, PLASTIC, MO-229WCCD-2, DFN-6 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 263K |
| 代理商： | LTC3542EDC |
LTC3542
10
3542f
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
OUT =+
06
1
2
1
.
To improve the frequency response, a feed-forward capaci-
tor, CF, may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin that provides
mode selection and frequency synchronization. Connect-
ing this pin to GND enables Burst Mode operation, which
provides the best low current efciency at the cost of a
higher output voltage ripple. Connecting this pin to VIN
selects pulse skip mode operation, which provides the
lowest output ripple at the cost of low current efciency.
The LTC3542 can also be synchronized to an external clock
signal with range from 1MHz to 3MHz by the MODE/SYNC
pin. During synchronization, the mode is set to pulse skip
and the top switch turn-on is synchronized to the falling
edge of the external clock.
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3542 circuits: 1) VIN quiescent current,
2) I2R loss and 3) switching loss. VIN quiescent current
loss dominates the power loss at very low load currents,
whereas the other two dominate at medium to high load
currents. In a typical efciency plot, the efciency curve
at very low load currents can be misleading since the
actual power loss is of no consequence as illustrated in
Figure 2.
1) The VIN quiescent current is the DC supply current given
in the Electrical Characteristics which excludes MOSFET
charging current. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT
2(RSW + RL)
APPLICATIO S I FOR ATIO
WU
UU
Figure 2. Power Loss vs Load Current
OUTPUT CURRENT (mA)
1
POWER
LOSS
(mW)
10
100
1000
0.1
10
100
1000
3542 F02
0.1
1
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VIN = 3.6V
Burst Mode OPERATION
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