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參數(shù)資料
| 型號： | LTC3534EGN#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 1150 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LTC3534EGN#TR |
LTC3534
14
3534f
APPLICATIONS INFORMATION
The output lter zero is given by:
fFILTER_ ZERO =
1
2
π RESR COUT
Hz
where RESR is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
fRHPZ =
VIN
2
π IOUT L1 VOUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth and
slower transient response. To ensure proper phase margin
using Type I compensation, the loop must be crossed over
a decade before the LC double pole. Referring to Figure
5, the unity-gain frequency of the error amplier utilizing
Type I compensation is given by:
fUG =
1
2
π R1CP1
Hz
Most applications demand an improved transient response
to allow a smaller output lter capacitor. To achieve a higher
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double-pole response of
the output lter. Referring to Figure 6, the location of the
poles and zeros are given by:
fPOLE1
1
2
π 5× 103 R1CP1
Hz
(which is extremely close to DC)
fZERO1 =
1
2
π RZ CP1
Hz
fZERO2 =
1
2
π R1CZ1
Hz
fPOLE2 =
1
2
π RZ CP2
Hz
where resistance is in Ohms and capacitance is in Far-
ads.
1V
R1
R2
3534 F05
FB
15
11
VC
CP1
VOUT
14
–
+
ERROR
AMP
1V
R1
R2
3534 F06
FB
15
11
VC
CP1
RZ
VOUT
14
CP2
CZ1
–
+
ERROR
AMP
Figure 5. Error Amplier with Type I Compensation
Figure 6. Error Amplier with Type III Compensation
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