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參數(shù)資料
| 型號： | LTC3525LESC6-3TRM |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.45 A SWITCHING REGULATOR, PDSO6 |
| 封裝： | PLASTIC, MO-203AB, SC-70, 6 PIN |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 235K |
| 代理商： | LTC3525LESC6-3TRM |
LTC3525L-3
6
3525lf
BLOCK DIAGRA
W
PI FU CTIO S
UU
U
SHDN (Pin 1): Logic Controlled Shutdown Input. Connect
to a voltage >0.88V to enable the LTC3525L-3. Connect to
a voltage <0.3V to disable the LTC3525L-3.
GND (Pins 2, 5): Ground.
VIN (Pin 3): Input Voltage. The LTC3525L-3 is powered
from VIN until VOUT exceeds VIN. Once VOUT is greater
than (VIN + 0.2V typical), it is powered from VOUT. Place
a ceramic bypass capacitor from VIN to GND. A minimum
value of 1F is recommended.
VOUT (Pin 4): Output Voltage Sense and the Output of the
Synchronous Rectier. Connect the output lter capacitor
from VOUT to GND, close to the IC. A minimum value of
10F ceramic is recommended. Use 22F for reduced
output ripple. The output disconnect feature disconnects
VOUT from VIN when SHDN is <0.3V.
SW (Pin 6): Switch Pin. Connect an inductor from this
pin to VIN. An internal antiringing resistor is connected
across SW and VIN after the inductor current has dropped
to zero to minimize EMI.
–
+
–
+
–
+
–
+
–
3
6
1
2
4
VREF
IPK
COMPARATOR
IVALLEY
COMPARATOR
SLEEP
COMPARATOR
INTEGRATOR
WAKE
TSD
IVAL
VOUT
VIN
SHDN
SW
IPK
ADJUST
GND
5
GND
FB
OFFSET
ADJUST
OFFSET
ADJUST
LOGIC
GATE DRIVERS
AND
ANTI-CROSS
CONDUCTION
WELL
SWITCH
VBEST
VREF
UVLO
THERMAL
SHUTDOWN
VB
SHUTDOWN
STARTUP
UVLO
SHUTDOWN
VREF
VSEL
VOUT
3525 BD
VIN
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PDF描述 |
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| LTC3525LESC6-3 | 0.45 A SWITCHING REGULATOR, PDSO6 |
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| LTC3526BEDC | 0.5 A SWITCHING CONTROLLER, 1300 kHz SWITCHING FREQ-MAX, PDSO6 |
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