參數(shù)資料
型號: LTC3416EFE
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 3.3-V CMOS 18-Bit Universal Bus Driver with 3-State Outputs 56-SSOP -40 to 85
中文描述: 8 A SWITCHING REGULATOR, 4000 kHz SWITCHING FREQ-MAX, PDSO20
封裝: 4.4 MM, PLASTIC, TSSOP-20
文件頁數(shù): 11/16頁
文件大小: 238K
代理商: LTC3416EFE
LTC3416
11
3416f
APPLICATIOU
W
U
U
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3416 as well as a timer for soft-start. Pulling the RUN/
SS pin below 0.5V places the LTC3416 in a low quiescent
current shutdown state (I
Q
< 1
μ
A).
The soft-start gradually raises the clamp on I
TH
. The full
current range becomes available on I
TH
after the voltage
on I
TH
reaches approximately 2V. The clamp on I
TH
is set
externally with a resistor and capacitor on the RUN/SS pin
as shown in Figure 1a. The soft-start duration can be
calculated by using the following formula:
t
R C In
V
–1 8
V
V
Seconds
(
SS
IN
IN
=
)
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1
. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
In most applications, the LTC3416 does not dissipate
much heat due to its high efficiency. But in applications
where the LTC3416 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
Figure 5. Dual Voltage System with Tracking
LTC3416
SGND
R1
3416 F05
R2
V
FB
TRACK
V
OUT1
LTC3416
SLAVE
MASTER
SGND
R3
R4
R5
V
FB
V
OUT2
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