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參數(shù)資料
| 型號： | LTC3112EDHD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 12 A SWITCHING REGULATOR, 825 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 5 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WJGD-2, DFN-16 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 651K |
| 代理商： | LTC3112EDHD#TRPBF |
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LTC3112
24
3112f
free parameter, CPOLE, to set the frequency fPOLE1 to the
common pole frequency of 250kHz.
C
POLE =
1
2
π 33kΩ
() 250kHz
()
22pF
Next, CFF can be chosen to set the second zero, fZERO2, to
the common zero frequency of 5kHz.
C
FF =
1
2
π 845kΩ
() 5kHz
()
40pF
In this case CFF was selected at 47pF giving a lower fre-
quency of 4kHz for the second zero. Finally, the resistor
value RFF can be chosen to place the second pole.
R
FF =
1
2
π 47pF
() 250kHz
()
13kΩ
A 10kΩ is chosen giving a 325kHz pole frequency. Now
that the pole frequencies, zero frequencies and gain of the
compensation network have been established, the next
step is to generate a Bode plot for the compensated error
amplier to conrm its gain and phase properties. A Bode
plot of the error amplier with the designed compensation
component values is shown in Figure 10. The Bode plot
conrms that the peak phase occurs near 30kHz and the
phase boost at that point is around 60°. In addition, the
gain at the peak phase frequency is –10db, close to the
design target.
APPLICATIONS INFORMATION
fC
FREQUENCY (Hz)
10
–200
GAIN
(dB)
PHASE
(DEG)
0
–50
100
1k
10k
100k
3112 F10
1M
–100
–150
50
100
–200
–150
0
–50
–100
50
100
GAIN
PHASE
Figure 10. Compensated Error Amplier Bode Plot.
The nal step in the design process is to compute the Bode
plot for the entire loop using the designed compensation
network and conrm its phase margin and crossover
frequency. The complete loop Bode plot for this example is
shown in Figure 11. The resulting loop crossover frequency
is 25kHz and the phase margin is approximately 60°. The
crossover frequency is a bit lower than the design target
of 35kHz, but farther away from the troublesome right
half plane zero.
FREQUENCY (Hz)
10
–60
GAIN
(dB)
PHASE
(DEG)
–40
–20
0
20
40
60
–180
fC
–120
–60
0
60
GAIN
120
180
100
1k
10k
100k
3112 F11
1M
PHASE
Figure 11. Complete Loop Bode Plot.
This feedback design example was done at 3.5VIN, 5VOUT,
and a 1A load current. The phase margin in boost mode
will decrease at lower VINs, higher VOUTs, load currents,
or inductor values due to the right half plane zero shifting
to a lower frequency.
As a reminder, the amount of power stage Q at the L-C
resonant frequency is highly dependent on the RS term
(series resistance) which includes the ESR of the inductor
and the LTC3112’s low RON MOSFETs. Lower total series
resistances give a higher Q, making the feedback design
more difcult. Higher series resistances lower the Q,
resulting in a lower loop cross over frequency.
The Bode plot for the complete loop should be checked over
all operating conditions and for variations in component
values to ensure that sufcient phase margin exists in all
cases. The stability of the loop should also be conrmed
via time domain simulation and by evaluating the transient
response of the converter in the actual circuit.
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| LTC3112EFE#TRPBF | 功能描述:IC REG BUCK BST SYNC ADJ 20TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關穩(wěn)壓器 系列:- 設計資源:Design Support Tool 標準包裝:1 系列:- 類型:升壓（升壓） 輸出類型:固定 輸出數(shù):1 輸出電壓:3V 輸入電壓:0.75 V ~ 2 V PWM 型:- 頻率 - 開關:- 電流 - 輸出:100mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-5 細型，TSOT-23-5 包裝:剪切帶 (CT) 供應商設備封裝:TSOT-23-5 其它名稱:AS1323-BTTT-30CT |
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