參數(shù)資料
型號: LTC2942CDCB-1#TRMPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PDSO6
封裝: 2 X 3 MM, LEAD FREE, PLASTIC, MO-229TBD, DFN-6
文件頁數(shù): 5/16頁
文件大?。?/td> 230K
代理商: LTC2942CDCB-1#TRMPBF
LTC2942-1
29421f
applicaTions inFormaTion
1000h at 1A current and 85°C ambient temperature; this
outperforms most types of discrete sense resistors except
those of the very high and ultrahigh stability variety. See
the Typical Performance Characteristics for expected
resistor drift performance under worst-case conditions.
Drift will be much slower at lower temperatures. Contact
LTC applications for more information.
Formostcoulombcounterapplicationsthisagingbehavior
of the integrated sense resistor is insignificant compared
to the change of battery capacity due to battery aging.
The LTC2942-1 is factory trimmed to optimum accuracy
whennew;forapplicationswhichrequirethebestpossible
coulomb count accuracy over the full product lifetime, the
coulomb counter gain can be adjusted in software. For
instance, if the error contribution of sense resistor drift
must be limited to ±1%, coulomb counts may be biased
high by 1% (use factor 1.01), and maximum operational
temperature and current then must be derated such that
sense resistor drift over product lifetime or calibration
intervals is less than –2%.
Applications employing the standard external resistor
LTC2942 with an external 50m sense resistor may be
upgraded to the pin-compatible LTC2942-1 by removing
the external sense resistor.
Voltage Drop Between SENSE+ and SENSE
The LTC2942-1 is trimmed for an effective internal resis-
tance of 50m , but the total pin-to-pin resistance (RPP),
consisting of the sense resistor in series with pin and bond
wire resistances, is somewhat higher. Assuming a sense
resistor temperature coefficient of about 3900ppm/K,
the total resistance between SENSE+ and SENSEat a
temperature T is typically:
RPP(T) = RPP(TNOM) [1 + 0.0039(T – TNOM)]
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
1 - 7
8
9
29421 F03
a6 - a0
b7 - b0
1 - 7
8
9
1 - 7
8
9
P
S
Figure 3. Data Transfer Over I2C or SMBus
FROM MASTER TO SLAVE
S
W
ADDRESS
REGISTER
DATA
FROM SLAVE TO MASTER
29421 F04
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
A
0
1100100
01h
FCh
0
P
Figure 4. Writing FCh to the LTC2942-1 Control Register (B)
S
W
ADDRESS
REGISTER
DATA
29421 F05
A
0
1100100
02h
F0h
01h
0
P
DATA
A
S
W
ADDRESS
REGISTER
S
29421 F06
A
ADDRESS
0
1100100
00h
1
0
1100100
0
P
R
1
A
01h
DATA
A
Figure 5. Writing F001h to the LTC2942-1
Accumulated Charge Register (C, D)
Figure 6. Reading the LTC2942-1 Status Register (A)
S
W
ADDRESS
REGISTER
S
29421 F07
A
ADDRESS
0
1100100
08h
1
0
1100100
0
P
R
0
A
F1h
DATA
24h
DATA
A
1
A
Figure 7. Reading the LTC2942-1 Voltage Register (I, J)
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