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參數(shù)資料
| 型號： | LTC2912HDDB-1#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 2 MM, PLASTIC, MO-229WECD-1, DFN-8 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 168K |
| 代理商： | LTC2912HDDB-1#TR |
LTC2912
9
2912fa
APPLICATIONS INFORMATION
When the VH input drops below its designed threshold,
the UV pin asserts low. When the input recovers above
its designed threshold, the UV output timer starts. If the
input remains above the designed threshold when the
timer nishes, the UV pin weakly pulls high. However, if
the input falls below its designed threshold during this
timeout period, the timer resets and restarts when the
input is above the designed threshold. The OV and OV
outputs behave as the UV output when LATCH is high
(LTC2912-1, LTC2912-3).
Selecting the UV/OV Timing Capacitor
The UV and OV timeout period (tUOTO) for the LTC2912
is adjustable to accommodate a variety of applications.
Connecting a capacitor, CTMR, between the TMR pin and
ground sets the timeout period. The value of capacitor
needed for a particular timeout period is:
CTMR = tUOTO 115 10–9 [F/s]
The Reset Timeout Period vs Capacitance graph found in
the Typical Performance Characteristics shows the desired
delay time as a function of the value of the timer capacitor
that must be used. The TMR pin must have a minimum
10pF load or be tied to VCC. For long timeout periods, the
only limitation is the availability of a large value capaci-
tor with low leakage. Capacitor leakage current must not
exceed the minimum TMR charging current of 1.3μA.Tying
the TMR pin to VCC bypasses the timeout period.
Undervoltage Lockout
When VCC falls below 2V, the LTC2912 asserts an
undervoltage lockout (UVLO) condition. During UVLO, UV
is asserted and pulled low while OV and OV are cleared
and blocked from asserting. When VCC rises above 2V, UV
follows the same timing procedure as an undervoltage
condition on the VH input.
Shunt Regulator
The LTC2912 has an internal shunt regulator. The VCC pin
operates as a direct supply input for voltages up to 6V. Under
this condition, the quiescent current of the device remains
below a maximum of 70μA. For VCC voltages higher than
6V, the device operates as a shunt regulator and should
have a resistance RZ between the supply and the VCC pin
to limit the current to no greater than 10mA.
When choosing this resistance value, select an appropriate
location on the I-V curve shown in the Typical Performance
Characteristics to accommodate any variations in VCC due
to changes in current through RZ.
UV, OV and OV Output Characteristics
The DC characteristics of the UV, OV and 0V pull-up and
pull-down strength are shown in the Typical Performance
Characteristics. Each pin has a weak internal pull-up to
VCC and a strong pull-down to ground. This arrangement
allows these pins to have open-drain behavior while pos-
sessing several other benecial characteristics. The weak
pull-up eliminates the need for an external pull-up resistor
when the rise time on the pin is not critical. On the other
hand, the open-drain conguration allows for wired-OR
connections, and is useful when more than one signal
needs to pull down on the output. VCC of 1V guarantees
a maximum VOL = 0.15V at UV.
At VCC = 1V, the weak pull-up current on OV is barely turned
on. Therefore, an external pull-up resistor of no more than
100k is recommended on the OV pin if the state and pull-up
strength of the OV pin is crucial at very low VCC.
Note however, by adding an external pull-up resistor, the
pull-up strength on the OV pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device must accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The UV, OV and OV outputs have strong pull-down capa-
bility. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(CLOAD):
tFALL ≈ 2.2 RPD CLOAD
where RPD is the on-resistance of the internal pull-down
transistor, typically 50Ω at VCC > 1V and at room tem-
perature (25°C). CLOAD is the external load capacitance
on the pin. Assuming a 150pF load capacitance, the fall
time is 16.5ns.
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