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參數(shù)資料
| 型號(hào)： | LTC2910HDHC#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | 5 X 3 MM, PLASTIC, MO-229WJED-1, DFN-16 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 520K |
| 代理商： | LTC2910HDHC#TR |
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LTC2910
6
2910fc
TMR PIN CAPACITANCE, CTMR (nF)
10
RST/
RST
TIMEOUT
PERIOD,
t
RST
(ms)
100
1000
10000
0.1
10
100
1000
2910 G12
1
SUPPLY VOLTAGE, VCC (V)
0
PULL-DOWN
CURRENT,
I
RST
(mA)
3
4
5
4
2910 G10
2
1
0
123
5
Vn = 0.45V
SEL = VCC
RST AT 150mV
RST AT 50mV
IRST/RST (mA)
0
RST
/RST
,V
OL
(V)
0.2
0.4
0.6
0.8
1.0
510
15
20
2910 G11
25
30
85°C
–40°C
25°C
PIN FUNCTIONS
DIS (Pin 13): Output Disable Input. Disables the RST and
RST output pins. When DIS is pulled high, the RST and
RST pins are not asserted except during a UVLO condition.
Pin has a weak (2μA) internal pull-down to GND. Leave
pin open if unused.
Exposed Pad (Pin 17, DFN Package): Exposed pad may
be left open or connected to device ground.
GND (Pin 9): Device Ground
REF (Pin 10): Buffered Reference Output. 1V reference
used for the offset of negative-monitoring applications.
The buffered reference sources and sinks up to 1mA. The
reference drives capacitive loads up to 1nF. Larger capacitive
loads may cause instability. Leave pin open if unused.
RST (Pin 11): Open-Drain Reset Logic Output. Asserts
high when any positive polarity input voltage is below
threshold or any negative polarity input voltage is above
threshold. Held high for an adjustable delay time after all
voltage inputs are valid. Pin has a weak pull-up to VCC and
may be pulled above VCC using an external pull-up. Leave
pin open if unused.
RST (Pin 12): Open-Drain Inverted Reset Logic Output.
Asserts low when any positive polarity input voltage is
below threshold or any negative polarity input voltage is
above threshold. Held low for an adjustable delay time after
all voltage inputs are valid. Pin has a weak pull-up to VCC
and may be pulled above VCC using an external pull-up.
Leave pin open if unused.
SEL (Pin 14): Input Polarity Select Three-State Input.
Connect to VCC, GND or leave unconnected in open state
to select one of three possible input polarity combinations
(refer to Table 1).
TMR (Pin 15): Reset Delay Timer. Attach an external ca-
pacitor (CTMR) of at least 10pF to GND to set a reset delay
time of 9ms/nF. A 1nF capacitor will generate an 8.5ms
reset delay time. Tie pin to VCC to bypass timer.
V1-V6 (Pin 1, 2, 3, 4, 5 & 6): Voltage Inputs 1 through 6.
When the voltage on this pin is below 0.5V, a reset condi-
tion is triggered. Tie pin to VCC if unused.
V7-V8 (Pin 7 & 8): Voltage Inputs 7 and 8. The polarity
of the input is selected by the state of the SEL pin (refer
TYPICAL PERFORMANCE CHARACTERISTICS
RST, ISINK vs VCC
RST/RST Voltage Output Low vs
Output Sink Current
Reset Timeout Period vs
Capacitance
Specications are at TA = 25°C and VCC = 3.3V
unless otherwise noted. (Note 2)
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