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參數(shù)資料
| 型號(hào)： | LTC2904IDDB8#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 2 MM, M0-229WECD-1, PLASTIC, DFN-8 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 179K |
| 代理商： | LTC2904IDDB8#PBF |
LTC2904/LTC2905
11
29045f
Figure 1 shows the desired delay time as a function of the
value of the timer capacitor that should be used:
As noted in the Power-Up and Power-Down sections the
circuits that drive RST and RST are powered by VCC.
During fault condition, VCC of at least 1V guarantees a
maximum VOL = 0.4V at RST. However, at VCC = 1V the
weak pull-up current on RST is barely turned on. There-
fore, an external pull-up resistor of no more than 100k is
recommended on the RST pin if the state and pull-up
strength of the RST pin is crucial at very low VCC.
Note however, by adding an external pull-up resistor, the
pull-up strength on the RST pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device needs to accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The RST and RST outputs have strong pull-down capabil-
ity. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(CLOAD):
tFALL ≈ 2.2 RPD CLOAD
where RPD is the on-resistance of the internal pull-down
transistor estimated to be typically 40
at room tempera-
ture (25
°C) and CLOAD is the external load capacitance on
the pin. Assuming a 150pF load capacitance, the fall time
is about 13ns.
The rise time, on the RST and RST pins is limited by weak
internal pull-up current sources to VCC. The following
formula estimates the output rise time (10% to 90%) at the
RST and RST pins:
tRISE ≈ 2.2 RPU CLOAD
where RPU is the on-resistance of the pull-up transistor.
Notice that this pull-up transistor is modeled as a 6
A
current source in the Block Diagram as a typical represen-
tation.
The on-resistance as a function of the VCC = Max (V1, V2)
voltage (for VCC > 1V) at room temperature is estimated as
Figure 1. Reset Time-Out Period vs Capacitance
Leaving the TMR pin open with no external capacitor
generates a reset time-out of approximately 200
s. For
long reset time-out, the only limitation is the availability of
large value capacitor with low leakage. The TMR capacitor
will never charge if the leakage current exceeds the mini-
mum TMR charging current of 2.1
A (typical).
RST and RST Output Characteristics
The DC characteristics of the RST and RST pull-up and
pull-down strength are shown in the Typical Performance
Characteristics section. Both RST and RST have a weak
internal pull-up to VCC = Max (V1, V2) and a strong pull-
down to ground.
The weak pull-up and strong pull-down arrangement allow
these two pins to have open-drain behavior while possess-
ing several other beneficial characteristics.
The weak pull-ups eliminate the need for external pull-up
resistors when the rise time on these pins is not critical. On
the other hand, the open-drain RST configuration allows
for wired-OR connections and can be useful when more
than one signal needs to pull down on the RST line.
APPLICATIO S I FOR ATIO
WU
UU
CTMR (FARAD)
10p
100p
1n
10n
100n
1
RESET
TIME
OUT
PERIOD,
t
RST
(ms)
29045 F01
10000
1000
100
10
1
0.1
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