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參數(shù)資料
| 型號(hào)： | LTC2900-1CMS#TRPFB |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 200K |
| 代理商： | LTC2900-1CMS#TRPFB |
11
LTC2900
2900f
APPLICATIO S I FOR ATIO
WU
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Although all four supply monitor comparators have built-
in glitch immunity, bypass capacitors on V1 and V2 are
recommended because the greater of V1 or V2 is also the
VCC for the device. Filter capacitors on the V3 and V4
inputs are allowed.
Power-Down
On power-down, once any of the VX inputs drop below
their threshold, RST is held at a logic low. A logic low of
0.4V is guaranteed until both V1 and V2 drop below 1V. If
the bandgap reference becomes invalid (VCC < 2V typ), the
part will reprogram once VCC rises above 2.4V max.
Monitor Output Rise and Fall Time Estimation
The RST output has strong pull-down capability. If the
external load capacitance (CLOAD) is known, output fall
time (10% to 90%) is estimated using:
tFALL ≈ 2.2 RPD CLOAD
where RPD is the on-resistance of the internal pull-down
transistor. The typical performance curve (VOL vs ISINK)
demonstrates that the pull-down current is somewhat
linear versus output voltage. Using the 25
°C curve, RPD is
estimated to be approximately 40
. Assuming a 150pF
load capacitance, the fall time is about 13.2ns.
Although the RST output of the LTC2900-1 is considered
to be “open-drain,” it does have weak pull-up capability
(see RST Pull-Up Current vs V2 curve). Output rise time
(10% to 90%) is estimated using:
tRISE ≈ 2.2 RPU CLOAD
where RPU is the on-resistance of the pull-up transistor.
The on-resistance as a function of the V2 voltage at room
temperature is estimated using:
R
V
PU =
610
21
5
–
with V2 = 3.3V, RPU is about 260k. Using 150pF for load
capacitance, the rise time is 86
s. If the output needs to
pull up faster and/or to a higher voltage, a smaller
external pull-up resistor may be used. Using a 10k pull-
up resistor, the rise time is reduced to 3.3
s for a 150pF
load capacitance.
The LTC2900-2 has an active pull-up to V2 on the RST
output. The typical performance curve (RST Pull-Up Cur-
rent vs V2 curve) demonstrates that the pull-up current is
somewhat linear versus the V2 voltage and RPU is esti-
mated to be approximately 625
. A 150pF load capaci-
tance makes the rise time about 206ns.
Selecting the Reset Timing Capacitor
The reset time-out period is adjustable in order to accom-
modate a variety of microprocessor applications. The
reset time-out period, tRST, is adjusted by connecting a
capacitor, CRT, between the CRT pin and ground. The value
of this capacitor is determined by:
CRT = tRST 217 10–9
with CRT in Farads and tRST in seconds. The CRT value per
millisecond of delay can also be expressed as CRT/ms =
217 (pF/ms).
Leaving the CRT pin unconnected will generate a mini-
mum reset time-out of approximately 50
s. Maximum
reset time-out is limited by the largest available low
leakage capacitor. The accuracy of the time-out period will
be affected by capacitor leakage (the nominal charging
current is 2
A) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
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