For more information www.linear.com/LTC2641 Note 1: Stresses beyond those lis" />
參數(shù)資料
型號(hào): LTC2642CDD-12#PBF
廠商: Linear Technology
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC DAC 12BIT VOUT 10-DFN
標(biāo)準(zhǔn)包裝: 121
設(shè)置時(shí)間: 1µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 600µW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-DFN(3x3)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1352 (CN2011-ZH PDF)
LTC2641/LTC2642
5
26412fc
For more information www.linear.com/LTC2641
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IIN
Digital Input Current
VIN = GND to VDD
l
±1
A
CIN
Digital Input Capacitance
(Note 6)
l
3
10
pF
VH
Hysteresis Voltage
0.15
V
Power Supply
VDD
Supply Voltage
l
2.7
5.5
V
IDD
Supply Current, VDD
Digital Inputs = 0V or VDD
l
120
200
A
PD
Power Dissipation
Digital Inputs = 0V or VDD, VDD = 5V
Digital Inputs = 0V or VDD, VDD = 3V
0.60
0.36
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
DIN Valid to SCLK Setup Time
l
10
ns
t2
DIN Valid to SCLK Hold Time
l
0
ns
t3
SCLK Pulse Width High
l
9
ns
t4
SCLK Pulse Width Low
l
9
ns
t5
CS Pulse High Width
l
10
ns
t6
LSB SCLK High to CS High
l
8
ns
t7
CS Low to SCLK High
l
8
ns
t8
CS High to SCLK Positive Edge
l
8
ns
t9
CLR Pulse Width Low
l
15
ns
fSCLK
SCLK Frequency
50% Duty Cycle
l
50
MHz
VDD High to CS Low (Power-Up Delay)
30
s
Note 4: ROUT tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.
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