- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗8634 > LTC2642ACDD-16#TRPBF (Linear Technology)IC DAC 16BIT VOUT 10-DFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LTC2642ACDD-16#TRPBF |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 4/24闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 16BIT VOUT 10-DFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 瑷�(sh猫)缃檪(sh铆)闁擄細 | 1µs |
| 浣嶆暩(sh霉)锛� | 16 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 600µW |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 10-WFDFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 10-DFN锛�3x3锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | * |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)鐣�(d膩ng)鍓嶇4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)
LTC2641/LTC2642
12
26412fc
For more information www.linear.com/LTC2641
operaTion
high-to-low transition, the data on DIN is loaded, MSB
first, into the shift register on each rising edge of the serial
clock input (SCLK). After 16 data bits have been loaded
into the serial input register, a low-to-high transition on
CS transfers the data to the 16-bit DAC latch, updating
the DAC output (see Figures 1a, 1b, 1c). While CS remains
high, the serial input shift register is disabled. If there
are less than 16 low-to-high transitions on SCLK while
CS remains low, the data will be corrupted, and must be
reloaded.Also,iftherearemorethan16low-to-hightransi-
tions on SCLK while CS remains low, only the last 16 data
bits loaded from DIN will be transferred to the DAC latch.
For the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two 鈥渄on鈥檛-care鈥� bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four 鈥渄on鈥檛-care鈥� bits must
follow the LSB (Figure 1c).
Power-On Reset
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC ouput comes up in a known state.
When VDD is first applied, the power-on reset circuit
sets the output of the LTC2641 to zero-scale (code 0).
The LTC2642 powers up to midscale (bipolar zero). De-
pending on the DAC number of bits, the midscale code
is: 32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048
(LTC2642-12).
Clearing the DAC
A 10ns (minimum) low pulse on the CLR pin asynchro-
nously clears the DAC latch to code zero (LTC2641) or to
midscale (LTC2642).
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
D15
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D14 D13 D12 D11 D10 D9
D8
DATA (16 BITS)
D7
D6
D5
D4
D3
D2
D1
D0
DAC
UPDATED
LSB
26412 F01a
D13
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D12 D11 D10 D9
D8
D7
D6
DATA (14 BITS + 2 DON鈥橳-CARE BITS)
D5
D4
D3
D2
D1
D0
X
DAC
UPDATED
LSB
26412 F01b
MSB
1
CS
SCLK
DIN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11 D10 D9
D8
D7
D6
DATA (12 BITS + 4 DON鈥橳-CARE BITS)
D5
D4
D3
D2
D1
D0
X
DAC
UPDATED
LSB
26412 F01c
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LTC2642ACMS-16#PBF | 鍔熻兘鎻忚堪:IC DAC 16BIT V-OUT 10-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:47 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:2µs 浣嶆暩(sh霉):14 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:55µW 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SSOP锛�0.209"锛�5.30mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SSOP 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆绘祦锛屽柈妤碉紱1 闆绘祦锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* |
| LTC2642ACMS-16#TRPBF | 鍔熻兘鎻忚堪:IC DAC 16BIT V-OUT 10-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:47 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:2µs 浣嶆暩(sh霉):14 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:55µW 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SSOP锛�0.209"锛�5.30mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SSOP 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆绘祦锛屽柈妤碉紱1 闆绘祦锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:* |
| LTC2642AIDD-16#PBF | 鍔熻兘鎻忚堪:IC DAC 16BIT VOUT 10-DFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
| LTC2642AIDD-16#TRPBF | 鍔熻兘鎻忚堪:IC DAC 16BIT VOUT 10-DFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
| LTC2642AIMS-16#PBF | 鍔熻兘鎻忚堪:IC DAC 16BIT V-OUT 10-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Fundamentals DAC Architectures 妯�(bi膩o)婧�(zh菙n)鍖呰:750 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:7µs 浣嶆暩(sh霉):16 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 闆诲闆绘簮:闆� ± 鍔熺巼鑰楁暎锛堟渶澶э級:100mW 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-LCC锛圝 褰㈠紩绶氾級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PLCC锛�11.51x11.51锛� 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆诲锛屽柈妤�锛�1 闆诲锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:143k |
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