參數資料
| 型號： | LTC2616IDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT I2C V-OUT 10-DFN |
| 標準包裝： | 121 |
| 設置時間： | 9µs |
| 位數： | 14 |
| 數據接口： | I²C |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 810µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸出數目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
LTC2606/LTC2616/LTC2626
5
26061626fb
TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
●
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
●
0.6
μs
tLOW
Low Period of the SCL Clock Pin
●
1.3
μs
tHIGH
High Period of the SCL Clock Pin
●
0.6
μs
tSU(STA)
Set-Up Time for a Repeated Start Condition
●
0.6
μs
tHD(DAT)
Data Hold Time
●
0
0.9
μs
tSU(DAT)
Data Set-Up Time
●
100
ns
tr
Rise Time of Both SDA and SCL Signals
(Note 9)
●
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 9)
●
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
●
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
●
1.3
μs
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
●
400
ns
t2
LDAC Low Pulse Width
●
20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are dened from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is dened from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full-scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and
3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 8: Maximum VIH = VCC(MAX) + 0.5V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specications apply to LTC2606/LTC2606-1, LTC2616/
LTC2616-1, LTC2626/LTC2626-1.
The ● denotes specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
ELECTRICAL CHARACTERISTICS The ● denotes specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
LTC2626/LTC2626-1
LTC2616/LTC2616-1
LTC2606/LTC2606-1
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AC Performance
tS
Settling Time (Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
77
9
7
9
10
μs
Settling Time for 1LSB Step
(Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
4.8
2.7
4.8
5.2
μs
Voltage Output Slew Rate
0.75
V/μs
Capacitive Load Driving
1000
pF
Glitch Impulse
At Mid-Scale Transition
12
nVs
Multiplying Bandwidth
180
kHz
en
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
μVP-P
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