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參數(shù)資料
| 型號(hào)： | LTC2609CGN#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 18/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT R-R QUAD 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 750µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁(yè)面： | 1351 (CN2011-ZH PDF) |
| 配用： | DC936A-ND - BOARD DAC LTC2609 |
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LTC2609/LTC2619/LTC2629
26091929fb
timing characteristics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
s
tLOW
Low Period of the SCL Clock Pin
l
1.3
s
tHIGH
High Period of the SCL Clock Pin
l
0.6
s
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
s
tHD(DAT)
Data Hold Time
l
0
0.9
s
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time of Both SDA and SCL Signals
(Note 7)
l
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 7)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
s
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
s
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
l
400
ns
t2
LDAC Low Pulse Width
l
20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating.
Note 4: Inferred from measurement at code kL (see Note 2) and at full-Scale.
Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: CB = capacitance of one bus line in pF.
Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with VCC = 5V, REFA = REFB = REFC
= REFD = 4.096V, with the measured DAC at mid-scale, unless otherwise
noted.
Note 11: RL = 2kΩ to GND or VCC.
Note 12: Guaranteed by design and not production tested.
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