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參數(shù)資料
| 型號： | LTC2602IMS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL R-R VOUT 8MSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 配用： | DC778A-ND - BOARD DAC LTC2602 |
11
LTC2602/LTC2612/LTC2622
2602fa
C3
COMMAND
ADDRESS
DATA (16 BITS)
C2
C1
C0
A3
A2
A1
A0
D13
D14
D15
D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
2602 TBL01
MSB
LSB
C3
COMMAND
ADDRESS
DATA (14 BITS + 2 DON’T-CARE BITS)
C2
C1
C0
A3
A2
A1
A0
D13 D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
2602 TBL02
MSB
LSB
C3
COMMAND
ADDRESS
DATA (12 BITS + 4 DON’T-CARE BITS)
C2
C1
C0
A3
A2
A1
A0
D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
X
XX
2602 TBL03
MSB
LSB
INPUT WORD (LTC2602)
INPUT WORD (LTC2612)
INPUT WORD (LTC2622)
OPERATIO
U
output pins are passively pulled to ground through indi-
vidual 90k
resistors. Input- and DAC-register contents
are not disturbed during power-down.
Either channel or both channels can be put into power-
down mode by using command 0100bin combination with
the appropriate DAC address, (n). The 16-bit data word is
ignored. The supply and reference currents are reduced by
approximately 50% for each DAC powered down; the
effective resistance at REF (pin 4) rises accordingly,
becoming a high-impedance input (typically > 1G
) when
both DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If one
of the two DACs is in a powered-down state prior to the
update command, the power-up delay is 5
s. If, on the
other hand, both DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power up delay time is
12
s (for VCC = 5V) or 30s (for VCC = 3V).
Voltage Outputs
Each of the two rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.050
when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25
typical channel resistance of the output devices; e.g.,
when sinking 1mA, the minimum output voltage = 25
1mA = 25mV. See the graph Headroom at Rails vs Output
Current in the Typical Performance Characteristics sec-
tion.
The amplifiers are stable driving capacitive loads of up to
1000pF.
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