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參數(shù)資料
| 型號： | LTC2495IUHF#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT W/PGA 38-QFN |
| 標準包裝： | 52 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-QFN（5x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1012A-C-ND - BOARD DELTA SIGMA ADC LTC2495 |
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LTC2495
2495fd
CONVERTER OPERATION
Converter Operation Cycle
The LTC2495 is a multichannel, low power, delta-sigma,
analog-to-digital converter with a 2-wire, I2C interface.
Its operation is made up of four states (see Figure 1).
The converter operating cycle begins with the conver-
sion, followed by the sleep state, and ends with the data
input/output cycle.
Initially, at power-up, the LTC2495 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption is
reduced by two orders of magnitude. The part remains in
the sleep state as long it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2495 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated by
a STOP condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 24
bits read out of the device).
Ease of Use
The LTC2495 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conver-
sion, immediately following a newly selected input or
mode, is valid and accurate to the full specifications of
the device.
The LTC2495 automatically performs offset and full-scale
calibrationeveryconversioncycleindependentoftheinput
channelselected.Thiscalibrationistransparenttotheuser
applications inForMation
Figure 1. State Transition Table
and has no effect on the operation cycle described above.
Theadvantageofcontinuouscalibrationisextremestability
ofoffsetandfull-scalereadingswithrespecttotime,supply
voltage variation, input channel and temperature drift.
Easy Drive Input Current Cancellation
The LTC2495 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
frontend.Aproprietaryfront-endpassivesamplingnetwork
transparently removes the differential input current. This
enables external RC networks and high impedance sen-
sors to directly interface to the LTC2495 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input im-
pedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC. Moreover, the
CONVERSION
SLEEP
2495 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24 BITS
DATA OUTPUT/INPUT
POWER-ON RESET
DEFAULT CONFIGURATION:
IN+ = CH0, IN– = CH1
50Hz/60Hz REJECTION
1x OUTPUT, GAIN = 1
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