If CS remains LOW longer than tEOCtest, t" />
參數(shù)資料
型號： LTC2449IUHF#TRPBF
廠商： Linear Technology
文件頁數(shù)： 13/28頁
文件大?。?/td> 0K
描述： IC ADC 24BIT HI SPEED 38QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 40mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個單端，雙極；8 個差分，雙極
配用： DC742A-ND - BOARD DELTA SIGMA ADC LTC2449
LTC2444/LTC2445/
LTC2448/LTC2449
20
2444589fb
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
APPLICATIO S I FOR ATIO
WU
U
Figure 8. Internal Serial Clock, Reduced Data Output Length
CS
SCK
SDI
SDO
BUSY
12345
6
15
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
BIT 31
2444 F09
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
TEST EOC
DON'T CARE
<tEOC(TEST)
VCC
FO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
F
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
BUSY
of SCK, see Figure 8. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. Thirteen
serial input data bits are required in order to properly
program the speed/resolution and input channel. If the
data output sequence is aborted prior to the 13th rising
edge of SCK, the new input data is ignored, and the
previously selected speed/resolution and channel are used
for the next conversion cycle. If a new channel is being
programmed, the rising edge of CS must come after the
14th falling edge of SCK in order to store the data input
sequence.
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