The sample rate f<" />
參數(shù)資料
型號(hào)： LTC2440IGN#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC DIFFER 24-BIT HS 16-SSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 24
采樣率（每秒）： 3.5k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 40mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC570A-ND - BOARD DELTA SIGMA ADC LTC2440
LTC2440
21
2440fd
APPLICATIONS INFORMATION
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
The sample rate fS and NULL fN, my also be adjusted by
driving the fO pin with an external oscillator. The sample
rate is fS = fEOSC /5, where fEOSC is the frequency of the
clock applied to fO. Combining a large OSR with a reduced
sample rate leads to notch frequencies fN near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to fO results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz lter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz can
be implemented using the LTC1799 (resistor set SOT-23
oscillator), see Figure 22. By oating pin 4 (DIV) of the
LTC1799, the output oscillator frequency is:
f
MHz
k
R
OSC
SET
=
10
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with RSET = 100k) to the fO pin on the LTC2440 with SDI
tied HIGH (OSR = 32768).
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8μA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
For example, if the OSR is programmed at the fastest rate
(OSR = 64, tCONV = 0.285ms) and the sleep state is 10ms,
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240μA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30μA. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/Speed)
and sleep mode duration (Power).
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
246
10
–100
–120
–140
NORMAL
MODE
REJECTION
(dB)
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