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參數(shù)資料
| 型號： | LTC2435IGN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/42頁 |
| 文件大小： | 0K |
| 描述： | IC CONV A/D 20BIT DIFF 16-SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2435/LTC2435-1
10
24351fc
For more information www.linear.com/LTC2435
pin FuncTions
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current
flow and VCC decoupling. Connect each one of these pins
to a ground plane through a low impedance connection.
All seven pins must be connected to ground for proper
operation.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10F tantalum capacitor in parallel with
0.1F ceramic capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The volt-
age on these pins can have any value between GND – 0.3V
and VCC + 0.3V. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5(VREF)
to 0.5(VREF). Outside this input range the converter
producesuniqueoverrangeandunderrangeoutputcodes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
fortheinternalserialinterfaceclockduringtheDataOutput
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. A weak internal pull-up is
automatically activated in Internal Serial Clock Operation
mode. The Serial Clock Operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controlstheADC’snotchfrequenciesandconversiontime.
When the FO pin is connected to VCC (LTC2435 only), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz (LTC2435)
or simultaneous 50Hz/60Hz (LTC2435-1). When FO is
driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
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