參數(shù)資料
型號(hào)： LTC2435CGN
廠商： Linear Technology
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC DIFF I/REF 20BIT 16-SSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 20
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2435/LTC2435-1
31
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
Inadditiontothisgainerror,theconverterINLperformance
is degraded by the reference source impedance. When FO
= LOW (internal oscillator and 60Hz notch), every 100Ω
of source resistance driving REF+ or REF– translates into
about 0.11ppm additional INL error. For the LTC2435,
when FO=HIGH(internaloscillatorand50Hznotch),every
100Ω of source resistance driving REF+ or REF– trans-
lates into about 0.092ppm additional INL error; and for
the LTC2435-1 operating with simultaneous 50Hz/60Hz
rejection, every 100Ω of source resistance leads to an
additional 0.10ppm of additional INL error. When FO is
driven by an external oscillator with a frequency fEOSC,
every 100Ω of source resistance driving REF+ or REF–
translates into about 0.73 10–6 fEOSCppm additional
INL error. Figure 25 shows the typical INL error due to the
sourceresistancedrivingtheREF+orREF–pinswhenlarge
CREF values are used. The effect of the source resistance
on the two reference pins is additive with respect to this
INL error. In general, matching of source impedance for
the REF+ and REF– pins does not help the gain or the INL
error. The user is thus advised to minimize the combined
Figure 25. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and
REF– for Large CREF Values (CREF ≥ 1F)
VINDIF/VREFDIF (V)
15
12
9
6
3
0
–3
–6
–9
–12
–15
INL
(ppm
OF
V
REF
)
2435 F25
0 0.1
–0.1
0.2
–0.2
0.3
–0.3
0.4
–0.4
0.5
–0.5
RSOURCE = 10k
RSOURCE = 5k
RSOURCE = 1k
VINCM = 0.5 (IN+ + IN–) = 2.5V
VCC = 5V
REF+ = 5V
REF– = GND
FO = GND
CREF = 10μF
TA = 25°C
source impedance driving the REF+ and REF– pins rather
than to try to match it.
The magnitude of the dynamic reference current depends
uponthesizeoftheverystableinternalsamplingcapacitors
andupontheaccuracyoftheconvertersamplingclock.The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05V typical and 0.5V
maximum full-scale error.
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