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參數(shù)資料
| 型號(hào)： | LTC2435CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/42頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DIFF I/REF 20BIT 16-SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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LTC2435/LTC2435-1
22
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore,theinternalserialclocktimingmodeisautomati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the conversion is over.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state. In order to allow the device to return to the
sleep state, CS must be pulled HIGH before the first ris-
ing edge of SCK. In the internal SCK timing mode, SCK
goes HIGH and the device begins outputting data at time
tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest
after EOC goes LOW (if CS is LOW during the falling edge
of EOC). The value of tEOCtest is 23s (LTC2435), 26s
(LTC2435-1) if the device is using its internal oscillator
(F0 = logic LOW or HIGH). If FO is driven by an external
oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state. The conversion result is held in the
internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this first rising edge of SCK and concludes after the
Figure 11. Internal Serial Clock, Single Cycle Operation
SDO
SCK
(INTERNAL)
CS
MSB
LSB
SIG
BIT 0
BIT 5
TEST EOC
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2435 F11
<tEOCtest
VCC
10k
Hi-Z
TEST EOC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
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