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LTC2414/LTC2418
11
241418fa
CS is HIGH. While in the sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins output-
ting the conversion result and inputting channel selection
bits. Taking CS high at this point will terminate the data
output state and start a new conversion. The channel
selection control bits are shifted in through SDI from the
Figure 1
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FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
Σ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
VCC
CH0
CH1
CH15
COM
IN+
IN–
MUX
SDO
SCK
REF+
REF –
CS
SDI
FO
(INT/EXT)
241418 F01
+
–
1.69k
SDO
241418 TA02
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
1.69k
SDO
241418 TA03
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
CONVERTER OPERATION
Converter Operation Cycle
The LTC2414/LTC2418 are multichannel, low power, delta-
sigma analog-to-digital converters with an easy-to-use
4-wire serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins with
the conversion, followed by the low power sleep state and
ends with the data input/output (see Figure 2). The 4-wire
interface consists of serial data input (SDI), serial data out-
put (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2414 or LTC2418 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
APPLICATIO S I FOR ATIO
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