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參數(shù)資料
型號(hào)： LTC2413IGN#PBF
廠商： Linear Technology
文件頁數(shù)： 20/44頁
文件大小： 0K
描述： IC A/D CONV 24BIT MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 1347 (CN2011-ZH PDF)
LTC2413
27
sn2413 2413fs
APPLICATIO S I FOR ATIO
WU
U
Reference Current
In a similar fashion, the LTC2413 samples the differential
reference pins REF+ and REF– transfering small amount of
charge to and from the external driving circuits, thus
produces a dynamic reference current. This current does
not change the converter offset but it may degrade the gain
and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When internal os-
cillator is used (FO = LOW), the typical differential input
resistance is 1.43M
which will generate a gain error of
approximately 0.35ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
external oscillator with a frequency fEOSC (external conver-
sion clock operation), the typical differential reference
resistance is 0.20 1012/fEOSC and each ohm of source
resistance drving REF+ or REF– will result in
2.47 10–6 fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF+ and REF– pins and external capacitance CREF con-
nected to these pins are shown in Figures 23, 24, 25
and 26.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When internal oscillator is used(FO = LOW), every 100 of
source impedance driving REF+ or REF– translates into
about 1.2ppm additional INL error. When FO is driven by
an external oscillator with a frequency fEOSC, every 100
of source resistance driving REF+ or REF– translates into
about 8.73 10–6 fEOSCppm additional INL error.
Figure 20. +FS Error vs RSOURCE at IN
+ or IN– (Large CIN)
Figure 21. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 22. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(
RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1F)
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(ppm
OF
V
REF
)
2413 F19
300
240
180
120
60
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2413 F21
0
–60
–120
–180
–240
–300
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
VINCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
OFFSET
ERROR
(ppm
OF
V
REF
)
2413 F22
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = IN– = VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
A
B
C
D
E
F
G
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