參數(shù)資料
型號: LTC2413CGN#PBF
廠商: Linear Technology
文件頁數(shù): 6/44頁
文件大小: 0K
描述: IC A/D CONV 24BIT MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝: 100
位數(shù): 24
采樣率(每秒): 6.8
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1347 (CN2011-ZH PDF)
LTC2413
14
sn2413 2413fs
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN+ and INpins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Simultaneous Frequency Rejection
The LTC2413 internal oscillator provides better than 87dB
normal mode rejection over the range of 49Hz to 61.2Hz as
shown in Figure 4. For this simultaneous 50Hz/60Hz
rejection, FO should be connected to GND.
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be sychronized with an outside source, the LTC2413
can operate with an external conversion clock. The conveter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods, tHEO and tLEO,
are observed.
Table 2. LTC2413 Output Data Format
Differential Input Voltage
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 0
VIN*
EOC
DMY
SIG
MSB
VIN* ≥ 0.5 VREF**
0
0110
0
0
0.5 VREF** – 1LSB
0
0101
1
1
0.25 VREF**
0
0101
0
0
0.25 VREF** – 1LSB
0
0100
1
1
0
0100
0
0
–1LSB
0
0011
1
1
– 0.25 VREF**
0
0011
0
0
– 0.25 VREF** – 1LSB
0
0010
1
1
– 0.5 VREF**
0
0010
0
0
VIN* < –0.5 VREF**
0
0001
1
1
*The differential input voltage VIN = IN+ – IN.
**The differential reference voltage VREF = REF+ – REF.
Figure 3. Output Data Timing
APPLICATIO S I FOR ATIO
WU
U
MSB
SIG
“0”
1
2
3
4
5
262732
BIT 0
BIT 27
BIT 5
LSB24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2413 F03
Hi-Z
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