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參數(shù)資料
| 型號(hào)： | LTC2392CLX-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SER/PAR 500K 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 135mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC1500A-B-ND - BOARD SAR ADC LTC2392-16 |
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LTC2392-16
16
239216fa
applications inFormation
down. The data from that conversion can be read after PD
= low is applied. In this mode power consumption drops
to a typical value of 175W from 110mW. This mode can
be used if the LTC2392-16 is inactive for a long period of
timeandtheuserwantstominimizethepowerdissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1F bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2392-16 will decrease
as the sampling frequency is reduced when nap mode is
activated. See Figure 7. In nap mode, a portion of the cir-
cuitry on the LTC2392-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
TIMING AND CONTROL
The LTC2392-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2392-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2392-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2392-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 1300ns. No
external adjustments are required and with a maximum
acquisition time of 685ns, a throughput performance of
500ksps is guaranteed.
DIGITAL INTERFACE
The LTC2392-16 allows both parallel and serial digital
interfaces.TheflexibleOVPsupplyallowstheLTC2392-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
Figure 7. Power Dissipation of the LTC2392-16
Decreases with Decreasing Sampling Frequency
SAMPLING FREQUENCY (kHz)
10
POWER
SUPPL
YCURRENT
(mA)
20
30
5
15
25
0.1
10
100
1000
239216 G15
0
1
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