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參數(shù)資料
| 型號： | LTC2380IMS-16#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/26頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 2MSPS 16-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | LTC2379- 18-/16-bit Fully-Differential SAR ADC Family Overview |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 22mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TFSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | * |
| 配用： | DC1783A-A-ND - BOARD SAR ADC LTC2380-16 |
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LTC2380-16
15
238016fa
reinitialize the ADC. No conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2380-16 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2380-16. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2380-16 powers down and begins acquiring the
input signal.
Internal Conversion Clock
The LTC2380-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 322ns. With a min-
imum acquisition time of 165ns, throughput performance
of 2Msps is guaranteed without any external adjustments.
Auto Power-Down
The LTC2380-16 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CNV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disable SDO and turn off SCK. The auto power-down feature
will reduce the power dissipation of the LTC2380-16 as
the sampling frequency is reduced. Since power is con-
sumed only during a conversion, the LTC2380-16 remains
APPLICATIONS INFORMATION
powered-down for a larger fraction of the conversion cycle
(tCYC) at lower sample rates, thereby reducing the average
power dissipation which scales with the sampling rate as
shown in Figure 12.
DIGITAL INTERFACE
The LTC2380-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2380-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
100MHz, a 2Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2380-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2380-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
SAMPLING RATE (kHz)
0
400
800
2000
1600
1200
0
POWER
SUPPL
Y
CURRENT
(mA)
5
4
2
1
3
8
7
6
238016 F12
IVDD
IREF
IOVDD
Figure 12. Power Supply Current of the LTC2380-16
Versus Sampling Rate
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