參數(shù)資料
型號： LTC2356CMSE-12
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝： PLASTIC, MSOP-10
文件頁數(shù)： 4/16頁
文件大小： 253K
代理商： LTC2356CMSE-12
4
LTC2356-12/LTC2356-14
2356f
SYMBOL
f
SAMPLE(MAX)
PARAMETER
Maximum Sampling Rate per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
Nearest SCK Edge Before CONV
Minimum High or Low CONV Pulse Width
SCK
↑
to Sample Mode
CONV
↑
to Hold Mode
16th SCK
↑
to CONV
≠
Interval (Affects Acquisition Period)
Delay from SCK to Valid Data
SCK
↑
to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
CONDITIONS
MIN
3.5
TYP
MAX
UNITS
MHz
●
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
●
286
10000
ns
ns
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Note 14)
●
15.872
16
2
3
0
4
4
1.2
45
18
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
8
6
2
2
TIW
U
range, otherwise specifications are at T
A
= 25
°
C. V
DD
= 3.3V
The
●
denotes the specifications which apply over the full operating temperature
POWER REQUIREW
range, otherwise specifications are at T
A
= 25
°
C. (Note 17)
SYMBOL
PARAMETER
V
DD
Supply Voltage
I
DD
Supply Current
U
The
●
denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
3.1
TYP
3.3
5.5
1.1
4
4
18
MAX
3.6
8
1.5
15
12
UNITS
V
Active Mode
Nap Mode
Sleep Mode (LTC2356-12)
Sleep Mode (LTC2356-14)
Active Mode with SCK in Fixed State (Hi or Lo)
●
●
mA
mA
μ
A
μ
A
mW
P
D
Power Dissipation
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and full-gain specifications are measured for a single-ended
A
IN+
input with A
IN–
grounded and using the internal 2.5V reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between A
IN+
and A
IN–
. Performance is specified with A
IN–
= 1.5V DC while
driving A
IN+
.
Note 9:
The absolute voltage at A
IN+
and A
IN–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns)
because the 2.2ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
16th rising clock and it is ended by the rising edge of convert.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10
μ
F capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops to 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock.
Note 17:
V
DD
= 3.3V, f
SAMPLE
= 3.5Msps.
Note 18:
The LTC2356-14 is measured and specified with 14-bit resolution
(1LSB = 152
μ
V) and the LTC2356-12 is measured and specified with
12-bit resolution (1LSB = 610
μ
V).
Note 19:
The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
相關PDF資料
PDF描述
LTC2356CMSE-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
LTC2356IMSE-12 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
LTC2356IMSE-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
LTC2428 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-TSSOP -40 to 85
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