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參數(shù)資料
| 型號： | LTC2356-14 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown |
| 中文描述： | 串行12-Bit/14-Bit，3.5Msps采樣ADC，帶有關(guān)斷 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 253K |
| 代理商： | LTC2356-14 |
14
LTC2356-12/LTC2356-14
2356f
internal reference. Note that, for slower conversion rates,
the Nap and Sleep modes can be used for substantial
reductions in power consumption.
DIGITAL INTERFACE
The LTC2356-12/LTC2356-14 has a 3-wire SPI-compatible
(Serial Protocol Interface) interface. The SCK and
CONV
inputs and SDO output implement this interface. The SCK
and CONV inputs accept swings from 3.3V logic and are
TTL compatible, if the logic swing does not exceed V
DD
. A
detailed description of the three serial port signals follows.
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC2356-12/
LTC2356-14 until the following 16 SCK rising edges have
occurred. It is necessary to have a minimum of 16 rising
edges of the clock input SCK between rising edges of
CONV. But to obtain maximum conversion speed (with a
63MHz SCK), it is necessary to allow two more clock
periods between conversions to allow 39ns of acquisition
time for the internal ADC sample-and-hold circuit. With 16
clock periods per conversion, the maximum conversion
rate is limited to 3.5Msps to allow 39ns for acquisition
time. In either case, the output data stream comes out
within the first 16 clock periods to ensure compatibility
with processor serial ports. The duty cycle of CONV can be
arbitrarily chosen to be used as a frame sync signal for the
processor serial port. A simple approach to generate
CONV is to create a pulse that is one SCK wide to drive the
LTC2356-12/LTC2356-14 and then buffer this signal with
the appropriate number of inverters to ensure the correct
delay driving the frame sync input of the processor
serial port. It is good practice to drive the LTC2356-12/
LTC2356-14 CONV input first to avoid digital noise inter-
ference during the sample-to-hold transition triggered by
CONV at the start of conversion. It is also good practice to
keep the width of the low portion of the CONV signal
greater than 15ns to avoid introducing glitches in the front
end of the ADC just before the sample-and-hold goes into
hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine
waves above 100kHz are sampled, the CONV signal must
have as little jitter as possible (10ps or less). The square
wave output of a common crystal clock module usually
meets this requirement . The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in Figure 8, the SCK and CONV inputs should be driven
first, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter in
these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will have
the same jitter of the DSP’s master clock.
The Typical Application Figure on page 16 shows a circuit
for level-shifting and squaring the output from an RF
signal generator or other low-jitter source. A single D-type
flip flop is used to generate the CONV signal to the
LTC2356-12/LTC2356-14. Re-timing the master clock
signal eliminates clock jitter introduced by the controlling
device (DSP, FPGA, etc.) Both the inverter and flip flop
must be treated as analog components and should be
powered from a clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking out
the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC2356-12/
LTC2356-14 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the Serial Data Output (SDO)
APPLICATIU
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