參數(shù)資料
型號(hào)： LTC2351IUH-12#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 1.5MSPS 32-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 16.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 12 個(gè)單端，單極；12 個(gè)單端，雙極；6 個(gè)差分，單極；6 個(gè)差分，雙極
配用： DC1278A-ND - BOARD SAR ADC LTC2351-14
LTC2351-12
8
235112fa
PIN FUNCTIONS
SDO (Pin 1): Three-State Serial Data Output. Each set
of six output data words represent the six analog input
channels at the start of the previous conversion. Data for
CH0 comes out rst and data for CH5 comes out last. Each
data word comes out MSB rst.
OGND (Pin 2): Ground Return for SDO Currents. Connect
to the solid ground plane.
OVDD (Pin 3): Power Supply for the SDO Pin. OVDD
must be no more than 300mV higher than VDD and can
be brought to a lower voltage to interface to low voltage
logic families. The unloaded high state at SDO is at the
potential of OVDD.
CH0+ (Pin 4):
Non-Inverting Channel 0. CH0+ operates
fully differentially with respect to CH0– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH0– (Pin 5):
Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These
ground pins must be tied directly to the solid ground plane
under the part. Analog signal currents ow through these
connections.
CH1+ (Pin 7):
Non-Inverting Channel 1. CH1+ operates
fully differentially with respect to CH1– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH1– (Pin 8):
Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH2+ (Pin 10):
Non-Inverting Channel 2. CH2+ operates
fully differentially with respect to CH2– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH2– (Pin 11):
Inverting Channel 2. CH2– operates fully
differentially with respect to CH2+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH3+ (Pin 14):
Non-Inverting Channel 3. CH3+ operates
fully differentially with respect to CH3– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH3– (Pin 15):
Inverting Channel 3. CH3– operates fully
differentially with respect to CH3+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH4+ (Pin 17):
Non-Inverting Channel 4. CH4+ operates
fully differentially with respect to CH4– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH4– (Pin 18):
Inverting Channel 4. CH4– operates fully
differentially with respect to CH4+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH5+ (Pin 20):
Non-Inverting Channel 5. CH5+ operates
fully differentially with respect to CH5– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH5– (Pin 21):
Inverting Channel 5. CH5– operates fully
differentially with respect to CH5+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
GND (PIN 22): Analog Ground for Reference. Analog
ground must be tied directly to the solid ground plane
under the part. Analog signal currents ow through this
connection. The 10μF reference bypass capacitor should
be returned to this pad.
VREF (Pin 23): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10μF ceramic capaci-
tor (or 10
μF tantalum in parallel with 0.1μF ceramic). Can
be overdriven by an external reference voltage between
2.55V and VDD, VCC.
VCC (Pin 24): 3V Positive Analog Supply. This pin sup-
plies 3V to the analog section. Bypass to the solid analog
ground plane with a 10μF ceramic capacitor (or 10μF
tantalum) in parallel with 0.1μF ceramic. Care should
be taken to place the 0.1μF bypass capacitor as close to
Pin 24 as possible. Pin 24 must be tied to Pin 25.
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