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參數(shù)資料
| 型號(hào)： | LTC2351HUH-12#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.5MSPS 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 16.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 12 個(gè)單端，單極；12 個(gè)單端，雙極；6 個(gè)差分，單極；6 個(gè)差分，雙極 |
| 配用： | DC1278A-ND - BOARD SAR ADC LTC2351-14 |
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LTC2351-12
5
235112fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specications apply for a single-ended CH0+
– CH5+ input with CH0– – CH5– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
dened as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is dened for the voltage difference
between CHx+ and CHx–, x = 0 to 5.
Note 9: The absolute voltage at CHx+ and CHx– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t9
SCK
↑ to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t11
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
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