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參數資料
| 型號： | LTC2306IDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12-BIT 2CH 500KSPS 10DFN |
| 標準包裝： | 2,500 |
| 位數： | 12 |
| 采樣率（每秒）： | 500k |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 14mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
LTC2302/LTC2306
10
23026fa
PIN FUNCTIONS
LTC2302
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1μF ceramic capacitor and a
10μF tantalum capacitor in parallel.
IN+, IN– (Pin 4, Pin 5):
Positive (IN+) and Negative (IN–)
Differential Analog Inputs.
VREF (Pin 6): Reference Input. Connect an external
reference at VREF. The range of the external reference is
0.1V to VDD.BypasstoGNDwithaminimum10μFtantalum
capacitor in parallel with a 0.1μF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
congures the ADC and is latched on the rising edge of
the rst 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
GND with a 0.1μF ceramic capacitor close to the pin. The
range of OVDD is 2.7V to 5.25V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
LTC2306
SDO (Pin 1): Three-State Serial Data Out. SDO outputs
the data from the previous conversion. SDO is shifted
out serially on the falling edge of each SCK pulse. SDO is
enabled by a low level on CONVST.
CONVST (Pin 2): Conversion Start. A rising edge at
CONVST begins a conversion. For best performance,
ensure that CONVST returns low within 40ns after the
conversion starts or after the conversion ends.
VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V.
Bypass VDD to GND with a 0.1μF ceramic capacitor and a
10μF tantalum capacitor in parallel.
CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog
Inputs. CH0, CH1 can be congured as single-ended or
differential input channels. See the Analog Input Multi-
plexer section.
VREF (Pin 6): Reference Input. Connect an external
reference at VREF.The range of the external reference is
0.1V to VDD.BypasstoGNDwithaminimum10μFtantalum
capacitor in parallel with a 0.1μF ceramic capacitor.
GND (Pin 7): Ground. All GND pins must be connected to
a solid ground plane.
SDI (Pin 8): Serial Data Input. The SDI serial bit stream
congures the ADC and is latched on the rising edge of
the rst 6 SCK pulses.
SCK (Pin 9): Serial Data Clock. SCK synchronizes the
serial data transfer. The serial data input at SDI is latched
on the rising edge of SCK. The serial data output at SDO
transitions on the falling edge of SCK.
OVDD (Pin 10): Output Driver Supply. Bypass OVDD to
OGND with a 0.1μF ceramic capacitor close to the pin.
The range of OVDD is 2.7V to 5.5V.
Exposed Pad (Pin 11): Exposed Pad Ground. Must be
soldered directly to ground plane.
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