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    參數(shù)資料
    型號(hào): LTC2294CUP#TRPBF
    廠商: Linear Technology
    文件頁數(shù): 7/24頁
    文件大?。?/td> 0K
    描述: IC ADC DUAL 12BIT 80MSPS 64QFN
    標(biāo)準(zhǔn)包裝: 2,000
    位數(shù): 12
    采樣率(每秒): 80M
    數(shù)據(jù)接口: 并聯(lián)
    轉(zhuǎn)換器數(shù)目: 2
    功率耗散(最大): 495mW
    電壓電源: 單電源
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 64-WFQFN 裸露焊盤
    供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 2 個(gè)單端,雙極; 2 個(gè)差分, 雙極
    LTC2294
    15
    2294fa
    APPLICATIO S I FOR ATIO
    WU
    UU
    Reference Operation
    Figure 9 shows the LTC2294 reference circuitry consisting
    of a 1.5V bandgap reference, a difference amplifier and
    switching and control circuit. The internal voltage refer-
    ence can be configured for two pin selectable input ranges
    of 2V (
    ±1Vdifferential)or1V(±0.5Vdifferential).Tyingthe
    SENSE pin to VDD selects the 2V range; tying the SENSE
    pin to VCM selects the 1V range.
    The 1.5V bandgap reference serves two functions: its
    output provides a DC bias point for setting the common
    mode voltage of any external input circuitry; additionally,
    the reference is used with a difference amplifier to gener-
    ate the differential reference levels needed by the internal
    ADC circuitry. An external bypass capacitor is required for
    the 1.5V reference output, VCM. This provides a high
    frequency low impedance path to ground for internal and
    external circuitry.
    The difference amplifier generates the high and low refer-
    ence for the ADC. High speed switching circuits are
    connected to these outputs and they must be externally
    bypassed. Each output has two pins. The multiple output
    pins are needed to reduce package inductance. Bypass
    capacitors must be connected as shown in Figure 9. Each
    ADC channel has an independent reference with its own
    bypass capacitors. The two channels can be used with the
    same or different input ranges.
    Other voltage ranges between the pin selectable ranges
    can be programmed with two external resistors as shown
    in Figure 10. An external reference can be used by applying
    its output directly or through a resistor divider to SENSE.
    It is not recommended to drive the SENSE pin with a logic
    device. The SENSE pin should be tied to the appropriate
    level as close to the converter as possible. If the SENSE pin
    is driven externally, it should be bypassed to ground as
    close to the device as possible with a 1
    F ceramic capacitor.
    For the best channel matching, connect an external reference
    to SENSEA and SENSEB.
    Figure 10. 1.5V Range ADC
    Figure 9. Equivalent Reference Circuit
    VCM
    REFH
    SENSE
    TIE TO VDD FOR 2V RANGE;
    TIE TO VCM FOR 1V RANGE;
    RANGE = 2 VSENSE FOR
    0.5V < VSENSE < 1V
    1.5V
    REFL
    2.2
    F
    2.2
    F
    INTERNAL ADC
    HIGH REFERENCE
    BUFFER
    0.1
    F
    2294 F09
    4
    DIFF AMP
    1
    F
    1
    F
    INTERNAL ADC
    LOW REFERENCE
    1.5V BANDGAP
    REFERENCE
    1V
    0.5V
    RANGE
    DETECT
    AND
    CONTROL
    LTC2294
    VCM
    SENSE
    1.5V
    0.75V
    2.2
    F
    12k
    1
    F
    12k
    2294 F10
    LTC2294
    Input Range
    The input range can be set based on the application. The
    2V input range will provide the best signal-to-noise perfor-
    mance while maintaining excellent SFDR. The 1V input
    range will have better SFDR performance, but the SNR will
    degrade by 4dB. See the Typical Performance Character-
    istics section.
    Driving the Clock Input
    The CLK inputs can be driven directly with a CMOS or TTL
    level signal. A sinusoidal clock can also be used along with
    a low jitter squaring circuit before the CLK pin (Figure 11).
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