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參數(shù)資料
| 型號： | LTC2285IUP#3CGPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, QFN-64 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 578K |
| 代理商： | LTC2285IUP#3CGPBF |
LTC2285IUP#3CGPBF
1
2285iup#3cgpbf
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual 14-Bit, 135Msps
Low Power 3.3V ADC
The LTC
2285IUP#3CGPBF is a 14-bit 135Msps, low
power dual 3.3V A/D converter designed for digitiz-
ing high frequency, wide dynamic range signals. The
LTC2285IUP#3CGPBF is perfect for demanding imaging
and communications applications with AC performance
that includes 72.2dB SNR and 82dB SFDR for signals at
the Nyquist frequency.
Typical DC specs include
±1.5LSB INL, ±0.6LSB DNL. The
transition noise is a low 1.3LSBRMS.
A single 3.3V supply allows low power operation. A
separate output supply allows the outputs to drive 0.5V
to 3.6V logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
SNR vs Input Frequency,
–1dB, 2V Range
n Integrated Dual 14-Bit ADCs
n Sample Rate: 135Msps
n Single 3.3V Supply (2.85V to 3.4V)
n Low Power: 954mW
n 72.4dB SNR, 88dB SFDR
n 110dB Channel Isolation at 100MHz
n Flexible Input: 1VP-P to 2VP-P Range
n 640MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
n 64-Pin (9mm
× 9mm) QFN Package
n Wireless and Wired Broadband Communication
n Imaging Systems
n Spectral Analysis
n Portable Instrumentation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
–
+
INPUT
S/H
ANALOG
INPUT A
ANALOG
INPUT B
CLK A
CLK B
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
OUTPUT
DRIVERS
OVDD
OGND
MUX
CLKOUT
D13A
D0A
OVDD
OGND
2285 TA01
D13B
D0B
–
+
OUTPUT
DRIVERS
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
OF
INPUT FREQUENCY (MHz)
0
65
SNR
(dBFS)
66
68
69
70
75
72
100
200
250
2285 TA01b
67
73
74
71
50
150
300
350
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2285IUPPBF | 制造商:Linear Technology 功能描述:ADC, Dual 14b 125Msps, 3V, LTC2285IUP |
| LTC2285IUP-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285IUP-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285IUP-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit, 135Msps Low Power 3.3V ADC |
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